| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/pmu/fuc/ |
| memx.fuc | 52 handler(VBLANK, 0x0001, 0x0000, #memx_func_wait_vblank)
168 // +00: head to wait for vblank on
206 // +00: head to wait for vblank on
|
| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_crt.c | 661 u32 vblank, vblank_start, vblank_end; local in function:intel_crt_load_detect
672 vblank_reg = VBLANK(pipe);
679 vblank = intel_uncore_read(uncore, vblank_reg);
684 vblank_start = (vblank & 0xfff) + 1;
685 vblank_end = ((vblank >> 16) & 0xfff) + 1;
696 /* Wait for next Vblank to substitue
751 /* restore vblank if necessary */
753 intel_uncore_write(uncore, vblank_reg, vblank);
|
| icl_dsi.c | 922 I915_WRITE(VBLANK(dsi_trans),
|
| intel_display.c | 1886 * which causes an apparent vblank timestamp jump when PIPEDSL
3518 * Vblank time updates from the shadow to live plane control register
3523 * event which is after the vblank start event, so we need to have a
3524 * wait-for-vblank between disabling the plane and the pipe.
5663 I915_READ(VBLANK(cpu_transcoder)));
6228 * We can only enable IPS after we enable a plane and wait for a vblank
6230 * a vblank wait.
6244 /* The bit only becomes 1 in the next vblank, so this wait here
6277 /* We need to wait for a vblank before we can disable the plane. */
6456 * Vblank time updates from the shadow to live plane control registe
14767 struct drm_vblank_crtc *vblank = &dev->vblank[drm_crtc_index(&crtc->base)]; local in function:intel_crtc_get_vblank_counter
18638 u32 vblank; member in struct:intel_display_error_state::intel_transcoder_error_state
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/i915/gvt/ |
| handlers.c | 2114 MMIO_D(VBLANK(TRANSCODER_A), D_ALL);
2124 MMIO_D(VBLANK(TRANSCODER_B), D_ALL);
2134 MMIO_D(VBLANK(TRANSCODER_C), D_ALL);
2144 MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL);
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| /src/sys/external/bsd/drm2/dist/drm/i915/ |
| i915_reg.h | 4309 #define VBLANK(trans) _MMIO_TRANS2(trans, _VBLANK_A)
|
