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    Searched refs:VCC (Results 1 - 17 of 17) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIWholeQuadMode.cpp 455 // for VCC, which can appear as the (implicit) input of a uniform branch,
864 .addReg(AMDGPU::VCC, RegState::Define)
872 // VCC represents lanes killed.
873 Register VCC = ST->isWave32() ? AMDGPU::VCC_LO : AMDGPU::VCC;
878 .addReg(VCC);
886 BuildMI(MBB, MI, DL, TII->get(AndN2Opc), Exec).addReg(Exec).addReg(VCC);
SIPeepholeSDWA.cpp 850 // implicit-def $vcc, implicit $exec
852 // 0, %26.sub1:vreg_64, implicit-def $vcc, implicit $vcc, implicit $exec
884 // Make sure VCC or its subregs are dead before MI.
886 auto Liveness = MBB.computeRegisterLiveness(TRI, AMDGPU::VCC, MI, 25);
889 // Check if VCC is referenced in range of (MI,MISucc].
892 if (I->modifiesRegister(AMDGPU::VCC, TRI))
936 if (SDst && (SDst->getReg() != AMDGPU::VCC &&
961 // FIXME: has SDWA but require handling of implicit VCC use
SIOptimizeExecMaskingPreRA.cpp 110 // $vcc = S_AND_B64 $exec, %cmp
113 // $vcc = S_ANDN2_B64 $exec, %cc
205 // and s_and_b64 if VCC or just unused if any other register.
320 CondReg = MCRegister::from(Wave32 ? AMDGPU::VCC_LO : AMDGPU::VCC);
SIInstrInfo.cpp 728 if (DestReg == AMDGPU::VCC) {
730 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), AMDGPU::VCC)
3498 // is vcc, and src0_modifiers and src1_modifiers are not set.
3550 // Set VCC operand with all flags from \p Orig, except for setting it as
3557 (Use.getReg() == AMDGPU::VCC || Use.getReg() == AMDGPU::VCC_LO)) {
3573 // For VOPC instructions, this is replaced by an implicit def of vcc.
3579 assert(((MI.getOperand(0).getReg() == AMDGPU::VCC) ||
3598 // replaced with an implicit read of vcc or vcc_lo. The implicit read
3599 // of vcc was already added during the initial BuildMI, but we
3600 // 1) may need to change vcc to vcc_lo to preserve the original registe
    [all...]
SIShrinkInstructions.cpp 601 unsigned VCCReg = ST.isWave32() ? AMDGPU::VCC_LO : AMDGPU::VCC;
739 // VOPC instructions can only write to the VCC register. We can't
740 // force them to use VCC here, because this is only one register and
742 // VCC, e.g. S_AND_B64 (vcc = V_CMP_...), (vcc = V_CMP_...)
744 // So, instead of forcing the instruction to write to VCC, we provide
745 // a hint to the register allocator to use VCC and then we will run
746 // this pass again after RA and shrink it if it outputs to VCC.
SIFoldOperands.cpp 259 auto Liveness = MBB->computeRegisterLiveness(&TRI, AMDGPU::VCC, MI, 16);
261 LLVM_DEBUG(dbgs() << "Not shrinking " << MI << " due to vcc liveness\n");
280 .addReg(AMDGPU::VCC, RegState::Kill);
SIRegisterInfo.cpp 493 Reserved.set(AMDGPU::VCC);
522 // This is to prevent BB vcc liveness errors.
2357 return isWave32 ? AMDGPU::VCC_LO : AMDGPU::VCC;
AMDGPUAsmPrinter.cpp 836 case AMDGPU::VCC:
1026 // 48 SGPRs - vcc, - flat_scr, -xnack
1154 // the registers which are usually reserved for vcc etc.
GCNHazardRecognizer.cpp 672 // v_div_fmas requires 4 wait states after a write to vcc from a VALU
678 int WaitStatesNeeded = getWaitStatesSinceDef(AMDGPU::VCC, IsHazardDefFn,
SIInsertWaitcnts.cpp 1458 // to vcc and then issued an smem load.
1500 } else if (Inst.definesRegister(AMDGPU::VCC)) {
1507 // of vcc back to vcc.
1512 // Writes to vcc while there's an outstanding smem read may get
1516 // Writes to vcc will fix any incorrect value in vccz.
1558 // Restore the vccz bit. Any time a value is written to vcc, the vcc
1560 // vcc and then writing it back to the register.
AMDGPUISelDAGToDAG.cpp 2280 // analyzed what generates the vcc value, so we do not know whether vcc
2288 // We could add an analysis of what generates the vcc value here and omit
2302 SDValue VCC = CurDAG->getCopyToReg(N->getOperand(0), SL, CondReg, Cond);
2305 VCC.getValue(0));
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Disassembler/
AMDGPUDisassembler.cpp 645 // VOPC - insert VCC register as sdst
646 insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC),
864 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in
868 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in
874 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in
1343 case 106: return createRegOperand(VCC);
1433 return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO);
1502 // = f(NEXT_FREE_SGPR + VCC + FLAT_SCRATCH + XNACK_MASK)
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/MCTargetDesc/
SIMCCodeEmitter.cpp 442 if (Reg != AMDGPU::VCC && Reg != AMDGPU::VCC_LO) {
AMDGPUInstPrinter.cpp 387 // Print default vcc/vcc_lo operand.
580 AMDGPU::VCC : AMDGPU::VCC_LO, O, MRI);
588 // Print default vcc/vcc_lo operand of VOPC.
591 (Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC) ||
695 // Print default vcc/vcc_lo operand of v_cndmask_b32_e32.
775 // Print default vcc/vcc_lo operand of VOP2b.
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AsmParser/
AMDGPUAsmParser.cpp 1191 /// \param VCCUsed [in] Whether VCC special SGPR is reserved.
2239 .Case("vcc", AMDGPU::VCC)
2331 Reg = AMDGPU::VCC;
3139 case AMDGPU::VCC:
3969 // Check if VCC register matches wavefront size
3972 return (FB[AMDGPU::FeatureWavefrontSize64] && Reg == AMDGPU::VCC) ||
7971 // VOP2b (v_add_u32, v_sub_u32 ...) dpp use "vcc" token.
8123 (Op.getReg() == AMDGPU::VCC || Op.getReg() == AMDGPU::VCC_LO)) {
8124 // VOP2b (v_add_u32, v_sub_u32 ...) sdwa use "vcc" token as dst
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/Disassembler/
ARMDisassembler.cpp 817 unsigned VCC = ARMVCC::None;
822 VCC = VPTBlock.getVPTPred();
852 VCCI = MI.insert(VCCI, MCOperand::createImm(VCC));
854 if (VCC == ARMVCC::None)
866 } else if (VCC != ARMVCC::None) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/
ARMAsmParser.cpp 900 struct VCCOp VCC;
951 return VCC.Val;
3581 Op->VCC.Val = CC;

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