1 /* $NetBSD: vce_4_0_sh_mask.h,v 1.2 2021/12/18 23:45:24 riastradh Exp $ */ 2 3 /* 4 * Copyright (C) 2017 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 #ifndef _vce_4_0_SH_MASK_HEADER 24 #define _vce_4_0_SH_MASK_HEADER 25 26 27 // addressBlock: vce0_vce_dec 28 //VCE_STATUS 29 #define VCE_STATUS__JOB_BUSY__SHIFT 0x0 30 #define VCE_STATUS__VCPU_REPORT__SHIFT 0x1 31 #define VCE_STATUS__UENC_BUSY__SHIFT 0x8 32 #define VCE_STATUS__VCE_CONFIGURATION__SHIFT 0x16 33 #define VCE_STATUS__VCE_INSTANCE_ID__SHIFT 0x18 34 #define VCE_STATUS__JOB_BUSY_MASK 0x00000001L 35 #define VCE_STATUS__VCPU_REPORT_MASK 0x000000FEL 36 #define VCE_STATUS__UENC_BUSY_MASK 0x00000100L 37 #define VCE_STATUS__VCE_CONFIGURATION_MASK 0x00C00000L 38 #define VCE_STATUS__VCE_INSTANCE_ID_MASK 0x03000000L 39 //VCE_VCPU_CNTL 40 #define VCE_VCPU_CNTL__CLK_EN__SHIFT 0x0 41 #define VCE_VCPU_CNTL__ED_ENABLE__SHIFT 0x1 42 #define VCE_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x12 43 #define VCE_VCPU_CNTL__ONE_CACHE_SURFACE_EN__SHIFT 0x15 44 #define VCE_VCPU_CNTL__CLK_EN_MASK 0x00000001L 45 #define VCE_VCPU_CNTL__ED_ENABLE_MASK 0x00000002L 46 #define VCE_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x00040000L 47 #define VCE_VCPU_CNTL__ONE_CACHE_SURFACE_EN_MASK 0x00200000L 48 //VCE_VCPU_CACHE_OFFSET0 49 #define VCE_VCPU_CACHE_OFFSET0__OFFSET__SHIFT 0x0 50 #define VCE_VCPU_CACHE_OFFSET0__OFFSET_MASK 0x0FFFFFFFL 51 //VCE_VCPU_CACHE_SIZE0 52 #define VCE_VCPU_CACHE_SIZE0__SIZE__SHIFT 0x0 53 #define VCE_VCPU_CACHE_SIZE0__SIZE_MASK 0x00FFFFFFL 54 //VCE_VCPU_CACHE_OFFSET1 55 #define VCE_VCPU_CACHE_OFFSET1__OFFSET__SHIFT 0x0 56 #define VCE_VCPU_CACHE_OFFSET1__OFFSET_MASK 0x0FFFFFFFL 57 //VCE_VCPU_CACHE_SIZE1 58 #define VCE_VCPU_CACHE_SIZE1__SIZE__SHIFT 0x0 59 #define VCE_VCPU_CACHE_SIZE1__SIZE_MASK 0x00FFFFFFL 60 //VCE_VCPU_CACHE_OFFSET2 61 #define VCE_VCPU_CACHE_OFFSET2__OFFSET__SHIFT 0x0 62 #define VCE_VCPU_CACHE_OFFSET2__OFFSET_MASK 0x0FFFFFFFL 63 //VCE_VCPU_CACHE_SIZE2 64 #define VCE_VCPU_CACHE_SIZE2__SIZE__SHIFT 0x0 65 #define VCE_VCPU_CACHE_SIZE2__SIZE_MASK 0x00FFFFFFL 66 //VCE_VCPU_CACHE_OFFSET3 67 #define VCE_VCPU_CACHE_OFFSET3__OFFSET__SHIFT 0x0 68 #define VCE_VCPU_CACHE_OFFSET3__OFFSET_MASK 0x0FFFFFFFL 69 //VCE_VCPU_CACHE_SIZE3 70 #define VCE_VCPU_CACHE_SIZE3__SIZE__SHIFT 0x0 71 #define VCE_VCPU_CACHE_SIZE3__SIZE_MASK 0x00FFFFFFL 72 //VCE_VCPU_CACHE_OFFSET4 73 #define VCE_VCPU_CACHE_OFFSET4__OFFSET__SHIFT 0x0 74 #define VCE_VCPU_CACHE_OFFSET4__OFFSET_MASK 0x0FFFFFFFL 75 //VCE_VCPU_CACHE_SIZE4 76 #define VCE_VCPU_CACHE_SIZE4__SIZE__SHIFT 0x0 77 #define VCE_VCPU_CACHE_SIZE4__SIZE_MASK 0x00FFFFFFL 78 //VCE_VCPU_CACHE_OFFSET5 79 #define VCE_VCPU_CACHE_OFFSET5__OFFSET__SHIFT 0x0 80 #define VCE_VCPU_CACHE_OFFSET5__OFFSET_MASK 0x0FFFFFFFL 81 //VCE_VCPU_CACHE_SIZE5 82 #define VCE_VCPU_CACHE_SIZE5__SIZE__SHIFT 0x0 83 #define VCE_VCPU_CACHE_SIZE5__SIZE_MASK 0x00FFFFFFL 84 //VCE_VCPU_CACHE_OFFSET6 85 #define VCE_VCPU_CACHE_OFFSET6__OFFSET__SHIFT 0x0 86 #define VCE_VCPU_CACHE_OFFSET6__OFFSET_MASK 0x0FFFFFFFL 87 //VCE_VCPU_CACHE_SIZE6 88 #define VCE_VCPU_CACHE_SIZE6__SIZE__SHIFT 0x0 89 #define VCE_VCPU_CACHE_SIZE6__SIZE_MASK 0x00FFFFFFL 90 //VCE_VCPU_CACHE_OFFSET7 91 #define VCE_VCPU_CACHE_OFFSET7__OFFSET__SHIFT 0x0 92 #define VCE_VCPU_CACHE_OFFSET7__OFFSET_MASK 0x0FFFFFFFL 93 //VCE_VCPU_CACHE_SIZE7 94 #define VCE_VCPU_CACHE_SIZE7__SIZE__SHIFT 0x0 95 #define VCE_VCPU_CACHE_SIZE7__SIZE_MASK 0x00FFFFFFL 96 //VCE_VCPU_CACHE_OFFSET8 97 #define VCE_VCPU_CACHE_OFFSET8__OFFSET__SHIFT 0x0 98 #define VCE_VCPU_CACHE_OFFSET8__OFFSET_MASK 0x0FFFFFFFL 99 //VCE_VCPU_CACHE_SIZE8 100 #define VCE_VCPU_CACHE_SIZE8__SIZE__SHIFT 0x0 101 #define VCE_VCPU_CACHE_SIZE8__SIZE_MASK 0x00FFFFFFL 102 //VCE_SOFT_RESET 103 #define VCE_SOFT_RESET__ECPU_SOFT_RESET__SHIFT 0x0 104 #define VCE_SOFT_RESET__UENC_SOFT_RESET__SHIFT 0x1 105 #define VCE_SOFT_RESET__FME_SOFT_RESET__SHIFT 0x2 106 #define VCE_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0x3 107 #define VCE_SOFT_RESET__DBF_SOFT_RESET__SHIFT 0x4 108 #define VCE_SOFT_RESET__ENT_SOFT_RESET__SHIFT 0x5 109 #define VCE_SOFT_RESET__TBE_SOFT_RESET__SHIFT 0x6 110 #define VCE_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x7 111 #define VCE_SOFT_RESET__CTL_SOFT_RESET__SHIFT 0x8 112 #define VCE_SOFT_RESET__IME_SOFT_RESET__SHIFT 0x9 113 #define VCE_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa 114 #define VCE_SOFT_RESET__SEM_SOFT_RESET__SHIFT 0xb 115 #define VCE_SOFT_RESET__DCAP_SOFT_RESET__SHIFT 0xc 116 #define VCE_SOFT_RESET__ACAP_SOFT_RESET__SHIFT 0xd 117 #define VCE_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0xe 118 #define VCE_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0xf 119 #define VCE_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT 0x10 120 #define VCE_SOFT_RESET__AVMUX_SOFT_RESET__SHIFT 0x13 121 #define VCE_SOFT_RESET__VREG_SOFT_RESET__SHIFT 0x14 122 #define VCE_SOFT_RESET__DCAP_FSM_SOFT_RESET__SHIFT 0x15 123 #define VCE_SOFT_RESET__VEP_SOFT_RESET__SHIFT 0x16 124 #define VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK 0x00000001L 125 #define VCE_SOFT_RESET__UENC_SOFT_RESET_MASK 0x00000002L 126 #define VCE_SOFT_RESET__FME_SOFT_RESET_MASK 0x00000004L 127 #define VCE_SOFT_RESET__MIF_SOFT_RESET_MASK 0x00000008L 128 #define VCE_SOFT_RESET__DBF_SOFT_RESET_MASK 0x00000010L 129 #define VCE_SOFT_RESET__ENT_SOFT_RESET_MASK 0x00000020L 130 #define VCE_SOFT_RESET__TBE_SOFT_RESET_MASK 0x00000040L 131 #define VCE_SOFT_RESET__LCM_SOFT_RESET_MASK 0x00000080L 132 #define VCE_SOFT_RESET__CTL_SOFT_RESET_MASK 0x00000100L 133 #define VCE_SOFT_RESET__IME_SOFT_RESET_MASK 0x00000200L 134 #define VCE_SOFT_RESET__IH_SOFT_RESET_MASK 0x00000400L 135 #define VCE_SOFT_RESET__SEM_SOFT_RESET_MASK 0x00000800L 136 #define VCE_SOFT_RESET__DCAP_SOFT_RESET_MASK 0x00001000L 137 #define VCE_SOFT_RESET__ACAP_SOFT_RESET_MASK 0x00002000L 138 #define VCE_SOFT_RESET__TAP_SOFT_RESET_MASK 0x00004000L 139 #define VCE_SOFT_RESET__LMI_SOFT_RESET_MASK 0x00008000L 140 #define VCE_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK 0x00010000L 141 #define VCE_SOFT_RESET__AVMUX_SOFT_RESET_MASK 0x00080000L 142 #define VCE_SOFT_RESET__VREG_SOFT_RESET_MASK 0x00100000L 143 #define VCE_SOFT_RESET__DCAP_FSM_SOFT_RESET_MASK 0x00200000L 144 #define VCE_SOFT_RESET__VEP_SOFT_RESET_MASK 0x00400000L 145 //VCE_RB_BASE_LO2 146 #define VCE_RB_BASE_LO2__RB_BASE_LO__SHIFT 0x6 147 #define VCE_RB_BASE_LO2__RB_BASE_LO_MASK 0xFFFFFFC0L 148 //VCE_RB_BASE_HI2 149 #define VCE_RB_BASE_HI2__RB_BASE_HI__SHIFT 0x0 150 #define VCE_RB_BASE_HI2__RB_BASE_HI_MASK 0xFFFFFFFFL 151 //VCE_RB_SIZE2 152 #define VCE_RB_SIZE2__RB_SIZE__SHIFT 0x4 153 #define VCE_RB_SIZE2__RB_SIZE_MASK 0x007FFFF0L 154 //VCE_RB_RPTR2 155 #define VCE_RB_RPTR2__RB_RPTR__SHIFT 0x4 156 #define VCE_RB_RPTR2__RB_RPTR_MASK 0x007FFFF0L 157 //VCE_RB_WPTR2 158 #define VCE_RB_WPTR2__RB_WPTR__SHIFT 0x4 159 #define VCE_RB_WPTR2__RB_WPTR_MASK 0x007FFFF0L 160 //VCE_RB_BASE_LO 161 #define VCE_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6 162 #define VCE_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L 163 //VCE_RB_BASE_HI 164 #define VCE_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0 165 #define VCE_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL 166 //VCE_RB_SIZE 167 #define VCE_RB_SIZE__RB_SIZE__SHIFT 0x4 168 #define VCE_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L 169 //VCE_RB_RPTR 170 #define VCE_RB_RPTR__RB_RPTR__SHIFT 0x4 171 #define VCE_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 172 //VCE_RB_WPTR 173 #define VCE_RB_WPTR__RB_WPTR__SHIFT 0x4 174 #define VCE_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 175 //VCE_RB_ARB_CTRL 176 #define VCE_RB_ARB_CTRL__RB_ARB_CTRL__SHIFT 0x0 177 #define VCE_RB_ARB_CTRL__VCE_CGTT_OVERRIDE__SHIFT 0x10 178 #define VCE_RB_ARB_CTRL__RB_ARB_CTRL_MASK 0x000001FFL 179 #define VCE_RB_ARB_CTRL__VCE_CGTT_OVERRIDE_MASK 0x00010000L 180 //VCE_CLOCK_GATING_A 181 #define VCE_CLOCK_GATING_A__CGC_CLK_ON_DELAY__SHIFT 0x0 182 #define VCE_CLOCK_GATING_A__CGC_CLK_OFF_DELAY__SHIFT 0x4 183 #define VCE_CLOCK_GATING_A__CGC_REG_AWAKE__SHIFT 0x11 184 #define VCE_CLOCK_GATING_A__CGC_CLK_ON_DELAY_MASK 0x0000000FL 185 #define VCE_CLOCK_GATING_A__CGC_CLK_OFF_DELAY_MASK 0x00000FF0L 186 #define VCE_CLOCK_GATING_A__CGC_REG_AWAKE_MASK 0x00020000L 187 //VCE_CLOCK_GATING_B 188 #define VCE_CLOCK_GATING_B__CGC_SYS_CLK_FORCE_ON__SHIFT 0x0 189 #define VCE_CLOCK_GATING_B__CGC_LMI_MC_CLK_FORCE_ON__SHIFT 0x1 190 #define VCE_CLOCK_GATING_B__CGC_LMI_UMC_CLK_FORCE_ON__SHIFT 0x2 191 #define VCE_CLOCK_GATING_B__CGC_UENC_CLK_FORCE_ON__SHIFT 0x3 192 #define VCE_CLOCK_GATING_B__CGC_VREG_CLK_FORCE_ON__SHIFT 0x4 193 #define VCE_CLOCK_GATING_B__CGC_ECPU_CLK_FORCE_ON__SHIFT 0x5 194 #define VCE_CLOCK_GATING_B__CGC_IH_CLK_FORCE_ON__SHIFT 0x6 195 #define VCE_CLOCK_GATING_B__CGC_SEM_CLK_FORCE_ON__SHIFT 0x7 196 #define VCE_CLOCK_GATING_B__CGC_CTLREG_CLK_FORCE_ON__SHIFT 0x8 197 #define VCE_CLOCK_GATING_B__CGC_MMSCH_CLK_FORCE_ON__SHIFT 0x9 198 #define VCE_CLOCK_GATING_B__CGC_SYS_CLK_FORCE_OFF__SHIFT 0x10 199 #define VCE_CLOCK_GATING_B__CGC_LMI_MC_CLK_FORCE_OFF__SHIFT 0x11 200 #define VCE_CLOCK_GATING_B__CGC_LMI_UMC_CLK_FORCE_OFF__SHIFT 0x12 201 #define VCE_CLOCK_GATING_B__CGC_UENC_CLK_FORCE_OFF__SHIFT 0x13 202 #define VCE_CLOCK_GATING_B__CGC_ECPU_CLK_FORCE_OFF__SHIFT 0x15 203 #define VCE_CLOCK_GATING_B__CGC_IH_CLK_FORCE_OFF__SHIFT 0x16 204 #define VCE_CLOCK_GATING_B__CGC_SEM_CLK_FORCE_OFF__SHIFT 0x17 205 #define VCE_CLOCK_GATING_B__CGC_MMSCH_CLK_FORCE_OFF__SHIFT 0x18 206 #define VCE_CLOCK_GATING_B__CGC_SYS_CLK_FORCE_ON_MASK 0x00000001L 207 #define VCE_CLOCK_GATING_B__CGC_LMI_MC_CLK_FORCE_ON_MASK 0x00000002L 208 #define VCE_CLOCK_GATING_B__CGC_LMI_UMC_CLK_FORCE_ON_MASK 0x00000004L 209 #define VCE_CLOCK_GATING_B__CGC_UENC_CLK_FORCE_ON_MASK 0x00000008L 210 #define VCE_CLOCK_GATING_B__CGC_VREG_CLK_FORCE_ON_MASK 0x00000010L 211 #define VCE_CLOCK_GATING_B__CGC_ECPU_CLK_FORCE_ON_MASK 0x00000020L 212 #define VCE_CLOCK_GATING_B__CGC_IH_CLK_FORCE_ON_MASK 0x00000040L 213 #define VCE_CLOCK_GATING_B__CGC_SEM_CLK_FORCE_ON_MASK 0x00000080L 214 #define VCE_CLOCK_GATING_B__CGC_CTLREG_CLK_FORCE_ON_MASK 0x00000100L 215 #define VCE_CLOCK_GATING_B__CGC_MMSCH_CLK_FORCE_ON_MASK 0x00000200L 216 #define VCE_CLOCK_GATING_B__CGC_SYS_CLK_FORCE_OFF_MASK 0x00010000L 217 #define VCE_CLOCK_GATING_B__CGC_LMI_MC_CLK_FORCE_OFF_MASK 0x00020000L 218 #define VCE_CLOCK_GATING_B__CGC_LMI_UMC_CLK_FORCE_OFF_MASK 0x00040000L 219 #define VCE_CLOCK_GATING_B__CGC_UENC_CLK_FORCE_OFF_MASK 0x00080000L 220 #define VCE_CLOCK_GATING_B__CGC_ECPU_CLK_FORCE_OFF_MASK 0x00200000L 221 #define VCE_CLOCK_GATING_B__CGC_IH_CLK_FORCE_OFF_MASK 0x00400000L 222 #define VCE_CLOCK_GATING_B__CGC_SEM_CLK_FORCE_OFF_MASK 0x00800000L 223 #define VCE_CLOCK_GATING_B__CGC_MMSCH_CLK_FORCE_OFF_MASK 0x01000000L 224 //VCE_RB_BASE_LO3 225 #define VCE_RB_BASE_LO3__RB_BASE_LO__SHIFT 0x6 226 #define VCE_RB_BASE_LO3__RB_BASE_LO_MASK 0xFFFFFFC0L 227 //VCE_RB_BASE_HI3 228 #define VCE_RB_BASE_HI3__RB_BASE_HI__SHIFT 0x0 229 #define VCE_RB_BASE_HI3__RB_BASE_HI_MASK 0xFFFFFFFFL 230 //VCE_RB_SIZE3 231 #define VCE_RB_SIZE3__RB_SIZE__SHIFT 0x4 232 #define VCE_RB_SIZE3__RB_SIZE_MASK 0x007FFFF0L 233 //VCE_RB_RPTR3 234 #define VCE_RB_RPTR3__RB_RPTR__SHIFT 0x4 235 #define VCE_RB_RPTR3__RB_RPTR_MASK 0x007FFFF0L 236 //VCE_RB_WPTR3 237 #define VCE_RB_WPTR3__RB_WPTR__SHIFT 0x4 238 #define VCE_RB_WPTR3__RB_WPTR_MASK 0x007FFFF0L 239 //VCE_SYS_INT_EN 240 #define VCE_SYS_INT_EN__VCE_SYS_INT_SEMA_WAIT_FAIL_TIMEOUT_EN__SHIFT 0x0 241 #define VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN__SHIFT 0x3 242 #define VCE_SYS_INT_EN__VCE_SYS_INT_SEMA_WAIT_FAIL_TIMEOUT_EN_MASK 0x00000001L 243 #define VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK 0x00000008L 244 //VCE_SYS_INT_ACK 245 #define VCE_SYS_INT_ACK__VCE_SYS_INT_SEMA_WAIT_FAIL_TIMEOUT_ACK__SHIFT 0x0 246 #define VCE_SYS_INT_ACK__VCE_SYS_INT_TRAP_INTERRUPT_ACK__SHIFT 0x3 247 #define VCE_SYS_INT_ACK__VCE_SYS_INT_SEMA_WAIT_FAIL_TIMEOUT_ACK_MASK 0x00000001L 248 #define VCE_SYS_INT_ACK__VCE_SYS_INT_TRAP_INTERRUPT_ACK_MASK 0x00000008L 249 //VCE_SYS_INT_STATUS 250 #define VCE_SYS_INT_STATUS__VCE_SYS_INT_SEMA_WAIT_FAIL_TIMEOUT_INT__SHIFT 0x0 251 #define VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT__SHIFT 0x3 252 #define VCE_SYS_INT_STATUS__VCE_SYS_INT_SEMA_WAIT_FAIL_TIMEOUT_INT_MASK 0x00000001L 253 #define VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT_MASK 0x00000008L 254 255 256 // addressBlock: vce0_ctl_dec 257 //VCE_UENC_CLOCK_GATING 258 #define VCE_UENC_CLOCK_GATING__CLOCK_ON_DELAY__SHIFT 0x0 259 #define VCE_UENC_CLOCK_GATING__CLOCK_OFF_DELAY__SHIFT 0x4 260 #define VCE_UENC_CLOCK_GATING__VEPCLK_FORCE_ON__SHIFT 0xc 261 #define VCE_UENC_CLOCK_GATING__IMECLK_FORCE_ON__SHIFT 0xd 262 #define VCE_UENC_CLOCK_GATING__FMECLK_FORCE_ON__SHIFT 0xe 263 #define VCE_UENC_CLOCK_GATING__TBECLK_FORCE_ON__SHIFT 0xf 264 #define VCE_UENC_CLOCK_GATING__DBFCLK_FORCE_ON__SHIFT 0x10 265 #define VCE_UENC_CLOCK_GATING__ENTCLK_FORCE_ON__SHIFT 0x11 266 #define VCE_UENC_CLOCK_GATING__LCMCLK_FORCE_ON__SHIFT 0x12 267 #define VCE_UENC_CLOCK_GATING__AVMCLK_FORCE_ON__SHIFT 0x13 268 #define VCE_UENC_CLOCK_GATING__DCAPCLK_FORCE_ON__SHIFT 0x14 269 #define VCE_UENC_CLOCK_GATING__ACAPCLK_FORCE_ON__SHIFT 0x15 270 #define VCE_UENC_CLOCK_GATING__ACAPCLK_FORCE_OFF__SHIFT 0x16 271 #define VCE_UENC_CLOCK_GATING__VEPCLK_FORCE_OFF__SHIFT 0x17 272 #define VCE_UENC_CLOCK_GATING__IMECLK_FORCE_OFF__SHIFT 0x18 273 #define VCE_UENC_CLOCK_GATING__FMECLK_FORCE_OFF__SHIFT 0x19 274 #define VCE_UENC_CLOCK_GATING__TBECLK_FORCE_OFF__SHIFT 0x1a 275 #define VCE_UENC_CLOCK_GATING__DBFCLK_FORCE_OFF__SHIFT 0x1b 276 #define VCE_UENC_CLOCK_GATING__ENTCLK_FORCE_OFF__SHIFT 0x1c 277 #define VCE_UENC_CLOCK_GATING__LCMCLK_FORCE_OFF__SHIFT 0x1d 278 #define VCE_UENC_CLOCK_GATING__AVMCLK_FORCE_OFF__SHIFT 0x1e 279 #define VCE_UENC_CLOCK_GATING__DCAPCLK_FORCE_OFF__SHIFT 0x1f 280 #define VCE_UENC_CLOCK_GATING__CLOCK_ON_DELAY_MASK 0x0000000FL 281 #define VCE_UENC_CLOCK_GATING__CLOCK_OFF_DELAY_MASK 0x00000FF0L 282 #define VCE_UENC_CLOCK_GATING__VEPCLK_FORCE_ON_MASK 0x00001000L 283 #define VCE_UENC_CLOCK_GATING__IMECLK_FORCE_ON_MASK 0x00002000L 284 #define VCE_UENC_CLOCK_GATING__FMECLK_FORCE_ON_MASK 0x00004000L 285 #define VCE_UENC_CLOCK_GATING__TBECLK_FORCE_ON_MASK 0x00008000L 286 #define VCE_UENC_CLOCK_GATING__DBFCLK_FORCE_ON_MASK 0x00010000L 287 #define VCE_UENC_CLOCK_GATING__ENTCLK_FORCE_ON_MASK 0x00020000L 288 #define VCE_UENC_CLOCK_GATING__LCMCLK_FORCE_ON_MASK 0x00040000L 289 #define VCE_UENC_CLOCK_GATING__AVMCLK_FORCE_ON_MASK 0x00080000L 290 #define VCE_UENC_CLOCK_GATING__DCAPCLK_FORCE_ON_MASK 0x00100000L 291 #define VCE_UENC_CLOCK_GATING__ACAPCLK_FORCE_ON_MASK 0x00200000L 292 #define VCE_UENC_CLOCK_GATING__ACAPCLK_FORCE_OFF_MASK 0x00400000L 293 #define VCE_UENC_CLOCK_GATING__VEPCLK_FORCE_OFF_MASK 0x00800000L 294 #define VCE_UENC_CLOCK_GATING__IMECLK_FORCE_OFF_MASK 0x01000000L 295 #define VCE_UENC_CLOCK_GATING__FMECLK_FORCE_OFF_MASK 0x02000000L 296 #define VCE_UENC_CLOCK_GATING__TBECLK_FORCE_OFF_MASK 0x04000000L 297 #define VCE_UENC_CLOCK_GATING__DBFCLK_FORCE_OFF_MASK 0x08000000L 298 #define VCE_UENC_CLOCK_GATING__ENTCLK_FORCE_OFF_MASK 0x10000000L 299 #define VCE_UENC_CLOCK_GATING__LCMCLK_FORCE_OFF_MASK 0x20000000L 300 #define VCE_UENC_CLOCK_GATING__AVMCLK_FORCE_OFF_MASK 0x40000000L 301 #define VCE_UENC_CLOCK_GATING__DCAPCLK_FORCE_OFF_MASK 0x80000000L 302 //VCE_UENC_REG_CLOCK_GATING 303 #define VCE_UENC_REG_CLOCK_GATING__MIFREGCLK_FORCE_ON__SHIFT 0x0 304 #define VCE_UENC_REG_CLOCK_GATING__IMEREGCLK_FORCE_ON__SHIFT 0x1 305 #define VCE_UENC_REG_CLOCK_GATING__FMEREGCLK_FORCE_ON__SHIFT 0x2 306 #define VCE_UENC_REG_CLOCK_GATING__TBEREGCLK_FORCE_ON__SHIFT 0x3 307 #define VCE_UENC_REG_CLOCK_GATING__DBFREGCLK_FORCE_ON__SHIFT 0x4 308 #define VCE_UENC_REG_CLOCK_GATING__ENTREGCLK_FORCE_ON__SHIFT 0x5 309 #define VCE_UENC_REG_CLOCK_GATING__LCMREGCLK_FORCE_ON__SHIFT 0x6 310 #define VCE_UENC_REG_CLOCK_GATING__RESERVED__SHIFT 0x7 311 #define VCE_UENC_REG_CLOCK_GATING__AVMREGCLK_FORCE_ON__SHIFT 0x8 312 #define VCE_UENC_REG_CLOCK_GATING__DCAPREGCLK_FORCE_ON__SHIFT 0x9 313 #define VCE_UENC_REG_CLOCK_GATING__VEPREGCLK_FORCE_ON__SHIFT 0xa 314 #define VCE_UENC_REG_CLOCK_GATING__MIFREGCLK_FORCE_ON_MASK 0x00000001L 315 #define VCE_UENC_REG_CLOCK_GATING__IMEREGCLK_FORCE_ON_MASK 0x00000002L 316 #define VCE_UENC_REG_CLOCK_GATING__FMEREGCLK_FORCE_ON_MASK 0x00000004L 317 #define VCE_UENC_REG_CLOCK_GATING__TBEREGCLK_FORCE_ON_MASK 0x00000008L 318 #define VCE_UENC_REG_CLOCK_GATING__DBFREGCLK_FORCE_ON_MASK 0x00000010L 319 #define VCE_UENC_REG_CLOCK_GATING__ENTREGCLK_FORCE_ON_MASK 0x00000020L 320 #define VCE_UENC_REG_CLOCK_GATING__LCMREGCLK_FORCE_ON_MASK 0x00000040L 321 #define VCE_UENC_REG_CLOCK_GATING__RESERVED_MASK 0x00000080L 322 #define VCE_UENC_REG_CLOCK_GATING__AVMREGCLK_FORCE_ON_MASK 0x00000100L 323 #define VCE_UENC_REG_CLOCK_GATING__DCAPREGCLK_FORCE_ON_MASK 0x00000200L 324 #define VCE_UENC_REG_CLOCK_GATING__VEPREGCLK_FORCE_ON_MASK 0x00000400L 325 //VCE_UENC_CLOCK_GATING_2 326 #define VCE_UENC_CLOCK_GATING_2__DBF2CLK_FORCE_ON__SHIFT 0x1 327 #define VCE_UENC_CLOCK_GATING_2__DBF2CLK_FORCE_OFF__SHIFT 0x10 328 #define VCE_UENC_CLOCK_GATING_2__DBF2CLK_FORCE_ON_MASK 0x00000002L 329 #define VCE_UENC_CLOCK_GATING_2__DBF2CLK_FORCE_OFF_MASK 0x00010000L 330 331 332 // addressBlock: vce0_vce_sclk_dec 333 //VCE_LMI_VCPU_CACHE_40BIT_BAR 334 #define VCE_LMI_VCPU_CACHE_40BIT_BAR__BAR__SHIFT 0x0 335 #define VCE_LMI_VCPU_CACHE_40BIT_BAR__BAR_MASK 0xFFFFFFFFL 336 //VCE_LMI_CTRL2 337 #define VCE_LMI_CTRL2__STALL_ARB__SHIFT 0x1 338 #define VCE_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x2 339 #define VCE_LMI_CTRL2__MASK_UMC_URGENT__SHIFT 0x3 340 #define VCE_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8 341 #define VCE_LMI_CTRL2__STALL_ARB_MASK 0x00000002L 342 #define VCE_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x00000004L 343 #define VCE_LMI_CTRL2__MASK_UMC_URGENT_MASK 0x00000008L 344 #define VCE_LMI_CTRL2__STALL_ARB_UMC_MASK 0x00000100L 345 //VCE_LMI_SWAP_CNTL3 346 #define VCE_LMI_SWAP_CNTL3__RD_MC_CID_SWAP__SHIFT 0x0 347 #define VCE_LMI_SWAP_CNTL3__RD_MC_CID_TRAN__SHIFT 0x14 348 #define VCE_LMI_SWAP_CNTL3__RD_MC_CID_URG__SHIFT 0x1a 349 #define VCE_LMI_SWAP_CNTL3__RD_MC_CID_SWAP_MASK 0x00000003L 350 #define VCE_LMI_SWAP_CNTL3__RD_MC_CID_TRAN_MASK 0x00100000L 351 #define VCE_LMI_SWAP_CNTL3__RD_MC_CID_URG_MASK 0x04000000L 352 //VCE_LMI_CTRL 353 #define VCE_LMI_CTRL__ASSERT_MC_URGENT__SHIFT 0xb 354 #define VCE_LMI_CTRL__MASK_MC_URGENT__SHIFT 0xc 355 #define VCE_LMI_CTRL__DATA_COHERENCY_EN__SHIFT 0xd 356 #define VCE_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15 357 #define VCE_LMI_CTRL__MIF_DATA_COHERENCY_EN__SHIFT 0x16 358 #define VCE_LMI_CTRL__VCPU_RD_CACHE_MISS_COUNT_EN__SHIFT 0x17 359 #define VCE_LMI_CTRL__VCPU_RD_CACHE_MISS_COUNT_RESET__SHIFT 0x18 360 #define VCE_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x00000800L 361 #define VCE_LMI_CTRL__MASK_MC_URGENT_MASK 0x00001000L 362 #define VCE_LMI_CTRL__DATA_COHERENCY_EN_MASK 0x00002000L 363 #define VCE_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x00200000L 364 #define VCE_LMI_CTRL__MIF_DATA_COHERENCY_EN_MASK 0x00400000L 365 #define VCE_LMI_CTRL__VCPU_RD_CACHE_MISS_COUNT_EN_MASK 0x00800000L 366 #define VCE_LMI_CTRL__VCPU_RD_CACHE_MISS_COUNT_RESET_MASK 0x01000000L 367 //VCE_LMI_SWAP_CNTL 368 #define VCE_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x0 369 #define VCE_LMI_SWAP_CNTL__WR_MC_CID_SWAP__SHIFT 0x2 370 #define VCE_LMI_SWAP_CNTL__WR_MC_CID_TRAN__SHIFT 0x14 371 #define VCE_LMI_SWAP_CNTL__WR_MC_CID_URG__SHIFT 0x1a 372 #define VCE_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x00000003L 373 #define VCE_LMI_SWAP_CNTL__WR_MC_CID_SWAP_MASK 0x00003FFCL 374 #define VCE_LMI_SWAP_CNTL__WR_MC_CID_TRAN_MASK 0x03F00000L 375 #define VCE_LMI_SWAP_CNTL__WR_MC_CID_URG_MASK 0xFC000000L 376 //VCE_LMI_SWAP_CNTL1 377 #define VCE_LMI_SWAP_CNTL1__VCPU_R_MC_SWAP__SHIFT 0x0 378 #define VCE_LMI_SWAP_CNTL1__RD_MC_CID_SWAP__SHIFT 0x2 379 #define VCE_LMI_SWAP_CNTL1__RD_MC_CID_TRAN__SHIFT 0x14 380 #define VCE_LMI_SWAP_CNTL1__RD_MC_CID_URG__SHIFT 0x1a 381 #define VCE_LMI_SWAP_CNTL1__VCPU_R_MC_SWAP_MASK 0x00000003L 382 #define VCE_LMI_SWAP_CNTL1__RD_MC_CID_SWAP_MASK 0x00003FFCL 383 #define VCE_LMI_SWAP_CNTL1__RD_MC_CID_TRAN_MASK 0x03F00000L 384 #define VCE_LMI_SWAP_CNTL1__RD_MC_CID_URG_MASK 0xFC000000L 385 //VCE_LMI_SWAP_CNTL2 386 #define VCE_LMI_SWAP_CNTL2__WR_MC_CID_SWAP__SHIFT 0x0 387 #define VCE_LMI_SWAP_CNTL2__WR_MC_CID_TRAN__SHIFT 0x14 388 #define VCE_LMI_SWAP_CNTL2__WR_MC_CID_URG__SHIFT 0x1a 389 #define VCE_LMI_SWAP_CNTL2__WR_MC_CID_SWAP_MASK 0x000000FFL 390 #define VCE_LMI_SWAP_CNTL2__WR_MC_CID_TRAN_MASK 0x00F00000L 391 #define VCE_LMI_SWAP_CNTL2__WR_MC_CID_URG_MASK 0x3C000000L 392 //VCE_LMI_CACHE_CTRL 393 #define VCE_LMI_CACHE_CTRL__VCPU_EN__SHIFT 0x0 394 #define VCE_LMI_CACHE_CTRL__VCPU_FLUSH__SHIFT 0x1 395 #define VCE_LMI_CACHE_CTRL__VCPU_EN_MASK 0x00000001L 396 #define VCE_LMI_CACHE_CTRL__VCPU_FLUSH_MASK 0x00000002L 397 //VCE_LMI_VCPU_CACHE_64BIT_BAR0 398 #define VCE_LMI_VCPU_CACHE_64BIT_BAR0__BAR__SHIFT 0x0 399 #define VCE_LMI_VCPU_CACHE_64BIT_BAR0__BAR_MASK 0x000000FFL 400 //VCE_LMI_VCPU_CACHE_64BIT_BAR1 401 #define VCE_LMI_VCPU_CACHE_64BIT_BAR1__BAR__SHIFT 0x0 402 #define VCE_LMI_VCPU_CACHE_64BIT_BAR1__BAR_MASK 0x000000FFL 403 //VCE_LMI_VCPU_CACHE_64BIT_BAR2 404 #define VCE_LMI_VCPU_CACHE_64BIT_BAR2__BAR__SHIFT 0x0 405 #define VCE_LMI_VCPU_CACHE_64BIT_BAR2__BAR_MASK 0x000000FFL 406 //VCE_LMI_VCPU_CACHE_64BIT_BAR3 407 #define VCE_LMI_VCPU_CACHE_64BIT_BAR3__BAR__SHIFT 0x0 408 #define VCE_LMI_VCPU_CACHE_64BIT_BAR3__BAR_MASK 0x000000FFL 409 //VCE_LMI_VCPU_CACHE_64BIT_BAR4 410 #define VCE_LMI_VCPU_CACHE_64BIT_BAR4__BAR__SHIFT 0x0 411 #define VCE_LMI_VCPU_CACHE_64BIT_BAR4__BAR_MASK 0x000000FFL 412 //VCE_LMI_VCPU_CACHE_64BIT_BAR5 413 #define VCE_LMI_VCPU_CACHE_64BIT_BAR5__BAR__SHIFT 0x0 414 #define VCE_LMI_VCPU_CACHE_64BIT_BAR5__BAR_MASK 0x000000FFL 415 //VCE_LMI_VCPU_CACHE_64BIT_BAR6 416 #define VCE_LMI_VCPU_CACHE_64BIT_BAR6__BAR__SHIFT 0x0 417 #define VCE_LMI_VCPU_CACHE_64BIT_BAR6__BAR_MASK 0x000000FFL 418 //VCE_LMI_VCPU_CACHE_64BIT_BAR7 419 #define VCE_LMI_VCPU_CACHE_64BIT_BAR7__BAR__SHIFT 0x0 420 #define VCE_LMI_VCPU_CACHE_64BIT_BAR7__BAR_MASK 0x000000FFL 421 //VCE_LMI_VCPU_CACHE_40BIT_BAR0 422 #define VCE_LMI_VCPU_CACHE_40BIT_BAR0__BAR__SHIFT 0x0 423 #define VCE_LMI_VCPU_CACHE_40BIT_BAR0__BAR_MASK 0xFFFFFFFFL 424 //VCE_LMI_VCPU_CACHE_40BIT_BAR1 425 #define VCE_LMI_VCPU_CACHE_40BIT_BAR1__BAR__SHIFT 0x0 426 #define VCE_LMI_VCPU_CACHE_40BIT_BAR1__BAR_MASK 0xFFFFFFFFL 427 //VCE_LMI_VCPU_CACHE_40BIT_BAR2 428 #define VCE_LMI_VCPU_CACHE_40BIT_BAR2__BAR__SHIFT 0x0 429 #define VCE_LMI_VCPU_CACHE_40BIT_BAR2__BAR_MASK 0xFFFFFFFFL 430 //VCE_LMI_VCPU_CACHE_40BIT_BAR3 431 #define VCE_LMI_VCPU_CACHE_40BIT_BAR3__BAR__SHIFT 0x0 432 #define VCE_LMI_VCPU_CACHE_40BIT_BAR3__BAR_MASK 0xFFFFFFFFL 433 //VCE_LMI_VCPU_CACHE_40BIT_BAR4 434 #define VCE_LMI_VCPU_CACHE_40BIT_BAR4__BAR__SHIFT 0x0 435 #define VCE_LMI_VCPU_CACHE_40BIT_BAR4__BAR_MASK 0xFFFFFFFFL 436 //VCE_LMI_VCPU_CACHE_40BIT_BAR5 437 #define VCE_LMI_VCPU_CACHE_40BIT_BAR5__BAR__SHIFT 0x0 438 #define VCE_LMI_VCPU_CACHE_40BIT_BAR5__BAR_MASK 0xFFFFFFFFL 439 //VCE_LMI_VCPU_CACHE_40BIT_BAR6 440 #define VCE_LMI_VCPU_CACHE_40BIT_BAR6__BAR__SHIFT 0x0 441 #define VCE_LMI_VCPU_CACHE_40BIT_BAR6__BAR_MASK 0xFFFFFFFFL 442 //VCE_LMI_VCPU_CACHE_40BIT_BAR7 443 #define VCE_LMI_VCPU_CACHE_40BIT_BAR7__BAR__SHIFT 0x0 444 #define VCE_LMI_VCPU_CACHE_40BIT_BAR7__BAR_MASK 0xFFFFFFFFL 445 446 447 // addressBlock: vce0_mmsch_dec 448 //VCE_MMSCH_VF_VMID 449 #define VCE_MMSCH_VF_VMID__VF_CTX_VMID__SHIFT 0x0 450 #define VCE_MMSCH_VF_VMID__VF_GPCOM_VMID__SHIFT 0x4 451 #define VCE_MMSCH_VF_VMID__VF_CTX_VMID_MASK 0x0000000FL 452 #define VCE_MMSCH_VF_VMID__VF_GPCOM_VMID_MASK 0x000000F0L 453 //VCE_MMSCH_VF_CTX_ADDR_LO 454 #define VCE_MMSCH_VF_CTX_ADDR_LO__VF_CTX_ADDR_LO__SHIFT 0x6 455 #define VCE_MMSCH_VF_CTX_ADDR_LO__VF_CTX_ADDR_LO_MASK 0xFFFFFFC0L 456 //VCE_MMSCH_VF_CTX_ADDR_HI 457 #define VCE_MMSCH_VF_CTX_ADDR_HI__VF_CTX_ADDR_HI__SHIFT 0x0 458 #define VCE_MMSCH_VF_CTX_ADDR_HI__VF_CTX_ADDR_HI_MASK 0xFFFFFFFFL 459 //VCE_MMSCH_VF_CTX_SIZE 460 #define VCE_MMSCH_VF_CTX_SIZE__VF_CTX_SIZE__SHIFT 0x0 461 #define VCE_MMSCH_VF_CTX_SIZE__VF_CTX_SIZE_MASK 0xFFFFFFFFL 462 //VCE_MMSCH_VF_GPCOM_ADDR_LO 463 #define VCE_MMSCH_VF_GPCOM_ADDR_LO__VF_GPCOM_ADDR_LO__SHIFT 0x6 464 #define VCE_MMSCH_VF_GPCOM_ADDR_LO__VF_GPCOM_ADDR_LO_MASK 0xFFFFFFC0L 465 //VCE_MMSCH_VF_GPCOM_ADDR_HI 466 #define VCE_MMSCH_VF_GPCOM_ADDR_HI__VF_GPCOM_ADDR_HI__SHIFT 0x0 467 #define VCE_MMSCH_VF_GPCOM_ADDR_HI__VF_GPCOM_ADDR_HI_MASK 0xFFFFFFFFL 468 //VCE_MMSCH_VF_GPCOM_SIZE 469 #define VCE_MMSCH_VF_GPCOM_SIZE__VF_GPCOM_SIZE__SHIFT 0x0 470 #define VCE_MMSCH_VF_GPCOM_SIZE__VF_GPCOM_SIZE_MASK 0xFFFFFFFFL 471 //VCE_MMSCH_VF_MAILBOX_HOST 472 #define VCE_MMSCH_VF_MAILBOX_HOST__DATA__SHIFT 0x0 473 #define VCE_MMSCH_VF_MAILBOX_HOST__DATA_MASK 0xFFFFFFFFL 474 //VCE_MMSCH_VF_MAILBOX_RESP 475 #define VCE_MMSCH_VF_MAILBOX_RESP__RESP__SHIFT 0x0 476 #define VCE_MMSCH_VF_MAILBOX_RESP__RESP_MASK 0xFFFFFFFFL 477 478 479 // addressBlock: vce0_vce_rb_pg_dec 480 //VCE_HW_VERSION 481 #define VCE_HW_VERSION__VCE_VERSION__SHIFT 0x0 482 #define VCE_HW_VERSION__VCE_CONFIGURATION__SHIFT 0x8 483 #define VCE_HW_VERSION__VCE_INSTANCE_ID__SHIFT 0xa 484 #define VCE_HW_VERSION__VCE_VERSION_MASK 0x000000FFL 485 #define VCE_HW_VERSION__VCE_CONFIGURATION_MASK 0x00000300L 486 #define VCE_HW_VERSION__VCE_INSTANCE_ID_MASK 0x00000C00L 487 488 489 490 #endif 491
Indexes created Thu Oct 02 14:10:14 GMT 2025