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    Searched refs:VCLK (Results 1 - 9 of 9) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
power_state.h 145 uint32_t VCLK;
185 unsigned long vclk; member in struct:pp_clock_engine_request
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
amdgpu_processpptables.c 765 ps->uvd_clocks.VCLK = le32_to_cpu(pnon_clock_info->ulVCLK);
768 ps->uvd_clocks.VCLK = 0;
1108 uvd_table->entries[i].vclk = ((unsigned long)entry->ucVClkHigh << 16)
amdgpu_smu10_hwmgr.c 798 smu10_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK;
amdgpu_smu7_hwmgr.c 3170 power_state->uvd_clocks.VCLK = 0;
3263 ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
3411 ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
4234 *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
amdgpu_smu8_hwmgr.c 147 if (clock <= ptable->entries[i].vclk)
155 if (clock >= ptable->entries[i].vclk)
518 (i < uvd_table->count) ? uvd_table->entries[i].vclk : 0;
602 clock = table->entries[level].vclk;
604 clock = table->entries[table->count - 1].vclk;
1393 smu8_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK;
1697 uint32_t sclk, vclk, dclk, ecclk, tmp, activity_percent; local
1731 vclk = uvd_table->entries[uvd_index].vclk;
    [all...]
amdgpu_vega10_hwmgr.c 1396 dep_mm_table->entries[i].vclk) {
1398 dep_mm_table->entries[i].vclk;
1998 "Failed to get VCLK clock settings from VBIOS!",
2074 if (dep_table->entries[i].vclk ==
3079 power_state->uvd_clocks.VCLK = 0;
3157 ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
4742 *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/
amdgpu_arcturus_ppt.c 145 CLK_MAP(VCLK, PPCLK_VCLK),
amdgpu_navi10_ppt.c 145 CLK_MAP(VCLK, PPCLK_VCLK),
amdgpu_vega20_ppt.c 159 CLK_MAP(VCLK, PPCLK_VCLK),
794 /* vclk */
800 pr_err("[SetupDefaultDpmTable] failed to get vclk dpm levels!");
805 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
2167 /* vclk */

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