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    Searched refs:VCS0 (Results 1 - 16 of 16) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/i915/
i915_pci.c 344 .engine_mask = BIT(RCS0) | BIT(VCS0),
354 .engine_mask = BIT(RCS0) | BIT(VCS0),
362 .engine_mask = BIT(RCS0) | BIT(VCS0), \
390 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
439 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
506 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
517 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
581 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
590 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
642 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1
    [all...]
i915_gpu_error.c 1174 case VCS0:
i915_drv.h 1660 ENGINE_INSTANCES_MASK(dev_priv, VCS0, I915_MAX_VCS)
i915_irq.c 3887 intel_engine_signal_breadcrumbs(dev_priv->engine[VCS0]);
  /src/sys/external/bsd/drm2/dist/drm/i915/gt/
intel_engine_types.h 115 VCS0,
119 #define _VCS(n) (VCS0 + (n))
intel_engine_user.c 213 [VIDEO_DECODE_CLASS] = { VCS0, I915_MAX_VCS },
intel_mocs.c 362 [VCS0] = __GEN9_VCS0_MOCS0,
intel_reset.c 323 [VCS0] = GEN6_GRDOM_MEDIA,
454 [VCS0] = GEN11_GRDOM_MEDIA,
intel_engine_cs.c 93 [VCS0] = {
intel_ring_submission.c 565 case VCS0:
intel_lrc.c 4358 [VCS0] = GEN8_VCS0_IRQ_SHIFT,
  /src/sys/external/bsd/drm2/dist/drm/i915/gvt/
mmio_context.c 159 [VCS0] = 0xc900,
346 [VCS0] = 0x4264,
406 [VCS0] = 0xc900,
execlist.c 57 [VCS0] = VCS_AS_CONTEXT_SWITCH,
cmd_parser.c 418 #define R_VCS1 BIT(VCS0)
598 [VCS0] = {
1098 [VCS0] = {
handlers.c 335 engine_mask |= BIT(VCS0);
1782 id = VCS0;
  /src/sys/external/bsd/drm2/dist/drm/i915/gem/
i915_gem_execbuffer.c 2260 GENMASK_ULL(VCS0 + I915_MAX_VCS - 1, VCS0));
2285 [I915_EXEC_BSD] = VCS0,

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