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    Searched refs:VECREDUCE_ADD (Results 1 - 13 of 13) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
ISDOpcodes.h 1219 VECREDUCE_ADD,
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
LegalizeVectorOps.cpp 477 case ISD::VECREDUCE_ADD:
881 case ISD::VECREDUCE_ADD:
SelectionDAGDumper.cpp 470 case ISD::VECREDUCE_ADD: return "vecreduce_add";
LegalizeIntegerTypes.cpp 208 case ISD::VECREDUCE_ADD:
1550 case ISD::VECREDUCE_ADD:
1998 case ISD::VECREDUCE_ADD:
2198 case ISD::VECREDUCE_ADD:
LegalizeVectorTypes.cpp 651 case ISD::VECREDUCE_ADD:
2216 case ISD::VECREDUCE_ADD:
4569 case ISD::VECREDUCE_ADD:
LegalizeDAG.cpp 1167 case ISD::VECREDUCE_ADD:
3768 case ISD::VECREDUCE_ADD:
SelectionDAG.cpp 378 case ISD::VECREDUCE_ADD:
SelectionDAGBuilder.cpp 9291 Res = DAG.getNode(ISD::VECREDUCE_ADD, dl, VT, Op1);
DAGCombiner.cpp 1728 case ISD::VECREDUCE_ADD:
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp 910 setTargetDAGCombine(ISD::VECREDUCE_ADD);
1057 setOperationAction(ISD::VECREDUCE_ADD, VT, Custom);
1063 setOperationAction(ISD::VECREDUCE_ADD, MVT::v2i64, Custom);
1152 setOperationAction(ISD::VECREDUCE_ADD, VT, Custom);
1512 setOperationAction(ISD::VECREDUCE_ADD, VT, Custom);
4640 case ISD::VECREDUCE_ADD:
10596 (Op.getOpcode() != ISD::VECREDUCE_ADD &&
10605 case ISD::VECREDUCE_ADD:
10635 case ISD::VECREDUCE_ADD:
11942 return DAG.getNode(ISD::VECREDUCE_ADD, DL, N->getValueType(0), Dot)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
TargetLoweringBase.cpp 827 setOperationAction(ISD::VECREDUCE_ADD, VT, Expand);
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVISelLowering.cpp 425 setOperationAction(ISD::VECREDUCE_ADD, MVT::i64, Custom);
499 setOperationAction(ISD::VECREDUCE_ADD, VT, Custom);
718 setOperationAction(ISD::VECREDUCE_ADD, VT, Custom);
2283 case ISD::VECREDUCE_ADD:
3492 case ISD::VECREDUCE_ADD:
5076 case ISD::VECREDUCE_ADD:
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelLowering.cpp 297 setOperationAction(ISD::VECREDUCE_ADD, VT, Legal);
991 setTargetDAGCombine(ISD::VECREDUCE_ADD);
15563 assert(N->getOpcode() == ISD::VECREDUCE_ADD);
15570 // vecreduce_add(sext(A, v8i32)) => VADDV.s16 A
15572 // vecreduce_add(mul(zext(A, v16i32), zext(B, v16i32))) => VMLADAV.u8 A, B
15774 return DAG.getNode(ISD::VECREDUCE_ADD, dl, ResVT, Ext);
17022 case ISD::VECREDUCE_ADD:

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