HomeSort by: relevance | last modified time | path
    Searched refs:VECREDUCE_AND (Results 1 - 13 of 13) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
ISDOpcodes.h 1221 VECREDUCE_AND,
1250 /// For example ISD::AND for ISD::VECREDUCE_AND.
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
LegalizeVectorOps.cpp 479 case ISD::VECREDUCE_AND:
883 case ISD::VECREDUCE_AND:
SelectionDAGDumper.cpp 472 case ISD::VECREDUCE_AND: return "vecreduce_and";
LegalizeIntegerTypes.cpp 210 case ISD::VECREDUCE_AND:
1552 case ISD::VECREDUCE_AND:
2000 case ISD::VECREDUCE_AND:
2200 case ISD::VECREDUCE_AND:
LegalizeVectorTypes.cpp 653 case ISD::VECREDUCE_AND:
2218 case ISD::VECREDUCE_AND:
4571 case ISD::VECREDUCE_AND:
LegalizeDAG.cpp 1169 case ISD::VECREDUCE_AND:
3770 case ISD::VECREDUCE_AND:
SelectionDAG.cpp 382 case ISD::VECREDUCE_AND:
5019 return getNode(ISD::VECREDUCE_AND, DL, VT, Operand);
DAGCombiner.cpp 1730 case ISD::VECREDUCE_AND:
21618 if (Opcode == ISD::VECREDUCE_AND || Opcode == ISD::VECREDUCE_OR) {
21619 unsigned NewOpcode = Opcode == ISD::VECREDUCE_AND
SelectionDAGBuilder.cpp 9297 Res = DAG.getNode(ISD::VECREDUCE_AND, dl, VT, Op1);
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVISelLowering.cpp 426 setOperationAction(ISD::VECREDUCE_AND, MVT::i64, Custom);
449 setOperationAction(ISD::VECREDUCE_AND, VT, Custom);
500 setOperationAction(ISD::VECREDUCE_AND, VT, Custom);
652 setOperationAction(ISD::VECREDUCE_AND, VT, Custom);
2289 case ISD::VECREDUCE_AND:
3502 case ISD::VECREDUCE_AND:
3516 assert((Op.getOpcode() == ISD::VECREDUCE_AND ||
3538 case ISD::VECREDUCE_AND:
5077 case ISD::VECREDUCE_AND:
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
TargetLoweringBase.cpp 829 setOperationAction(ISD::VECREDUCE_AND, VT, Expand);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp 1153 setOperationAction(ISD::VECREDUCE_AND, VT, Custom);
1180 setOperationAction(ISD::VECREDUCE_AND, VT, Custom);
1329 setOperationAction(ISD::VECREDUCE_AND, VT, Custom);
1513 setOperationAction(ISD::VECREDUCE_AND, VT, Custom);
4641 case ISD::VECREDUCE_AND:
10592 bool OverrideNEON = Op.getOpcode() == ISD::VECREDUCE_AND ||
10607 case ISD::VECREDUCE_AND:
17774 case ISD::VECREDUCE_AND: {
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelLowering.cpp 303 setOperationAction(ISD::VECREDUCE_AND, VT, Custom);
9658 case ISD::VECREDUCE_AND: BaseOpcode = ISD::AND; break;
9926 case ISD::VECREDUCE_AND:

Completed in 144 milliseconds