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    Searched refs:VECREDUCE_SMIN (Results 1 - 13 of 13) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
ISDOpcodes.h 1225 VECREDUCE_SMIN,
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
LegalizeVectorOps.cpp 483 case ISD::VECREDUCE_SMIN:
887 case ISD::VECREDUCE_SMIN:
SelectionDAGDumper.cpp 476 case ISD::VECREDUCE_SMIN: return "vecreduce_smin";
LegalizeIntegerTypes.cpp 214 case ISD::VECREDUCE_SMIN:
1556 case ISD::VECREDUCE_SMIN:
2006 case ISD::VECREDUCE_SMIN:
2204 case ISD::VECREDUCE_SMIN:
LegalizeVectorTypes.cpp 657 case ISD::VECREDUCE_SMIN:
2222 case ISD::VECREDUCE_SMIN:
4575 case ISD::VECREDUCE_SMIN:
LegalizeDAG.cpp 1173 case ISD::VECREDUCE_SMIN:
3774 case ISD::VECREDUCE_SMIN:
SelectionDAG.cpp 390 case ISD::VECREDUCE_SMIN:
5011 case ISD::VECREDUCE_SMIN:
SelectionDAGBuilder.cpp 9309 Res = DAG.getNode(ISD::VECREDUCE_SMIN, dl, VT, Op1);
DAGCombiner.cpp 1734 case ISD::VECREDUCE_SMIN:
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
TargetLoweringBase.cpp 833 setOperationAction(ISD::VECREDUCE_SMIN, VT, Expand);
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVISelLowering.cpp 430 setOperationAction(ISD::VECREDUCE_SMIN, MVT::i64, Custom);
504 setOperationAction(ISD::VECREDUCE_SMIN, VT, Custom);
720 setOperationAction(ISD::VECREDUCE_SMIN, VT, Custom);
2287 case ISD::VECREDUCE_SMIN:
3500 case ISD::VECREDUCE_SMIN:
5082 case ISD::VECREDUCE_SMIN:
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp 1059 setOperationAction(ISD::VECREDUCE_SMIN, VT, Custom);
1158 setOperationAction(ISD::VECREDUCE_SMIN, VT, Custom);
1320 setOperationAction(ISD::VECREDUCE_SMIN, MVT::v2i64, Custom);
1521 setOperationAction(ISD::VECREDUCE_SMIN, VT, Custom);
4645 case ISD::VECREDUCE_SMIN:
10613 case ISD::VECREDUCE_SMIN:
10639 case ISD::VECREDUCE_SMIN:
16699 case ISD::VECREDUCE_SMIN:
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelLowering.cpp 300 setOperationAction(ISD::VECREDUCE_SMIN, VT, Legal);
12507 } else if ((TrueVal->getOpcode() == ISD::VECREDUCE_SMIN ||
12508 FalseVal->getOpcode() == ISD::VECREDUCE_SMIN) &&
12531 case ISD::VECREDUCE_SMIN:

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