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    Searched refs:VECREDUCE_UMIN (Results 1 - 13 of 13) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
ISDOpcodes.h 1227 VECREDUCE_UMIN,
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
LegalizeVectorOps.cpp 485 case ISD::VECREDUCE_UMIN:
889 case ISD::VECREDUCE_UMIN:
SelectionDAGDumper.cpp 478 case ISD::VECREDUCE_UMIN: return "vecreduce_umin";
LegalizeIntegerTypes.cpp 216 case ISD::VECREDUCE_UMIN:
1558 case ISD::VECREDUCE_UMIN: Res = PromoteIntOp_VECREDUCE(N); break;
2010 case ISD::VECREDUCE_UMIN:
2206 case ISD::VECREDUCE_UMIN: ExpandIntRes_VECREDUCE(N, Lo, Hi); break;
LegalizeVectorTypes.cpp 659 case ISD::VECREDUCE_UMIN:
2224 case ISD::VECREDUCE_UMIN:
4577 case ISD::VECREDUCE_UMIN:
LegalizeDAG.cpp 1175 case ISD::VECREDUCE_UMIN:
3776 case ISD::VECREDUCE_UMIN:
SelectionDAG.cpp 394 case ISD::VECREDUCE_UMIN:
5017 case ISD::VECREDUCE_UMIN:
DAGCombiner.cpp 1736 case ISD::VECREDUCE_UMIN:
21620 ? ISD::VECREDUCE_UMIN : ISD::VECREDUCE_UMAX;
SelectionDAGBuilder.cpp 9315 Res = DAG.getNode(ISD::VECREDUCE_UMIN, dl, VT, Op1);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
TargetLoweringBase.cpp 835 setOperationAction(ISD::VECREDUCE_UMIN, VT, Expand);
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVISelLowering.cpp 432 setOperationAction(ISD::VECREDUCE_UMIN, MVT::i64, Custom);
506 setOperationAction(ISD::VECREDUCE_UMIN, VT, Custom);
722 setOperationAction(ISD::VECREDUCE_UMIN, VT, Custom);
2286 case ISD::VECREDUCE_UMIN:
3498 case ISD::VECREDUCE_UMIN:
5083 case ISD::VECREDUCE_UMIN:
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp 1061 setOperationAction(ISD::VECREDUCE_UMIN, VT, Custom);
1156 setOperationAction(ISD::VECREDUCE_UMIN, VT, Custom);
1322 setOperationAction(ISD::VECREDUCE_UMIN, MVT::v2i64, Custom);
1523 setOperationAction(ISD::VECREDUCE_UMIN, VT, Custom);
4647 case ISD::VECREDUCE_UMIN:
10617 case ISD::VECREDUCE_UMIN:
10643 case ISD::VECREDUCE_UMIN:
16701 case ISD::VECREDUCE_UMIN:
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelLowering.cpp 301 setOperationAction(ISD::VECREDUCE_UMIN, VT, Legal);
12501 if ((TrueVal->getOpcode() == ISD::VECREDUCE_UMIN ||
12502 FalseVal->getOpcode() == ISD::VECREDUCE_UMIN) &&
12530 case ISD::VECREDUCE_UMIN:

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