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    Searched refs:VECS0 (Results 1 - 17 of 17) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/i915/
i915_pci.c 517 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
581 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
590 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
642 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
659 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
718 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
739 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
789 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
796 .engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
830 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2)
    [all...]
i915_gpu_error.c 1177 case VECS0:
i915_drv.h 1662 ENGINE_INSTANCES_MASK(dev_priv, VECS0, I915_MAX_VECS)
  /src/sys/external/bsd/drm2/dist/drm/i915/gvt/
mmio_context.c 134 {VECS0, RING_EXCC(VEBOX_RING_BASE), 0xffff, false}, /* 0x1a028 */
162 [VECS0] = 0xcb00,
349 [VECS0] = 0x4270,
409 [VECS0] = 0xcb00,
execlist.c 59 [VECS0] = VECS_AS_CONTEXT_SWITCH,
cmd_parser.c 422 #define R_VECS BIT(VECS0)
620 [VECS0] = {
1108 [VECS0] = {
handlers.c 343 engine_mask |= BIT(VECS0);
1791 id = VECS0;
  /src/sys/external/bsd/drm2/dist/drm/i915/gt/
intel_engine_types.h 120 VECS0,
122 #define _VECS(n) (VECS0 + (n))
intel_engine_user.c 214 [VIDEO_ENHANCEMENT_CLASS] = { VECS0, I915_MAX_VECS },
intel_mocs.c 364 [VECS0] = __GEN9_VECS0_MOCS0,
intel_gt_irq.c 449 if (HAS_ENGINE(gt->i915, VECS0)) {
intel_reset.c 325 [VECS0] = GEN6_GRDOM_VECS,
458 [VECS0] = GEN11_GRDOM_VECS,
intel_engine_cs.c 128 [VECS0] = {
intel_ring_submission.c 568 case VECS0:
intel_rps.c 1579 intel_engine_signal_breadcrumbs(gt->engine[VECS0]);
intel_lrc.c 4360 [VECS0] = GEN8_VECS_IRQ_SHIFT,
  /src/sys/external/bsd/drm2/dist/drm/i915/gem/
i915_gem_execbuffer.c 2286 [I915_EXEC_VEBOX] = VECS0

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