| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 1149 {ISD::VECTOR_SHUFFLE, MVT::v2i32, 1},
1150 {ISD::VECTOR_SHUFFLE, MVT::v2f32, 1},
1151 {ISD::VECTOR_SHUFFLE, MVT::v2i64, 1},
1152 {ISD::VECTOR_SHUFFLE, MVT::v2f64, 1},
1153 {ISD::VECTOR_SHUFFLE, MVT::v4i16, 1},
1154 {ISD::VECTOR_SHUFFLE, MVT::v8i8, 1},
1156 {ISD::VECTOR_SHUFFLE, MVT::v4i32, 1},
1157 {ISD::VECTOR_SHUFFLE, MVT::v4f32, 1},
1158 {ISD::VECTOR_SHUFFLE, MVT::v8i16, 1},
1159 {ISD::VECTOR_SHUFFLE, MVT::v16i8, 1}}
[all...] |
| ARMISelLowering.cpp | 184 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
261 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
331 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
440 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
980 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
7031 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
7093 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
7167 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef"
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 550 /// VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as
551 /// VEC1/VEC2. A VECTOR_SHUFFLE node also contains an array of constant int
557 VECTOR_SHUFFLE,
|
| SelectionDAGNodes.h | 1483 : SDNode(ISD::VECTOR_SHUFFLE, Order, dl, getSDVTList(VT)), Mask(M) {}
1528 return N->getOpcode() == ISD::VECTOR_SHUFFLE;
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGDumper.cpp | 290 case ISD::VECTOR_SHUFFLE: return "vector_shuffle";
|
| DAGCombiner.cpp | 1715 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
4901 if (HandOpcode == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG) {
12637 N0->getOpcode() == ISD::VECTOR_SHUFFLE && N0.hasOneUse() &&
18159 // (insert_vector_elt (vector_shuffle X, Y), (extract_vector_elt X, N),
18161 // --> (vector_shuffle X, Y) and variations where shuffle operands may be
18163 if (Vec.getOpcode() == ISD::VECTOR_SHUFFLE && Vec.hasOneUse() &&
18618 // Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT.
18624 if (IndexC && VecOp.getOpcode() == ISD::VECTOR_SHUFFLE) {
18658 TLI.isOperationExpand(ISD::VECTOR_SHUFFLE, VecVT)) {
18726 // Perform only after legalization to ensure build_vector / vector_shuffle
[all...] |
| SelectionDAG.cpp | 740 case ISD::VECTOR_SHUFFLE: {
1775 "Invalid VECTOR_SHUFFLE");
1918 AddNodeIDNode(ID, ISD::VECTOR_SHUFFLE, getVTList(VT), Ops);
2531 case ISD::VECTOR_SHUFFLE: {
2619 case ISD::VECTOR_SHUFFLE: {
2812 case ISD::VECTOR_SHUFFLE: {
3724 case ISD::VECTOR_SHUFFLE: {
6034 case ISD::VECTOR_SHUFFLE:
|
| LegalizeVectorTypes.cpp | 66 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
950 case ISD::VECTOR_SHUFFLE:
2997 case ISD::VECTOR_SHUFFLE:
|
| LegalizeDAG.cpp | 2998 case ISD::VECTOR_SHUFFLE: {
4571 case ISD::VECTOR_SHUFFLE: {
|
| TargetLowering.cpp | 840 case ISD::VECTOR_SHUFFLE: {
1127 case ISD::VECTOR_SHUFFLE: {
2703 case ISD::VECTOR_SHUFFLE: {
|
| LegalizeIntegerTypes.cpp | 101 case ISD::VECTOR_SHUFFLE:
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonISelLoweringHVX.cpp | 81 setOperationAction(ISD::VECTOR_SHUFFLE, ByteV, Legal);
82 setOperationAction(ISD::VECTOR_SHUFFLE, ByteW, Legal);
136 setPromoteTo(ISD::VECTOR_SHUFFLE, T, ByteV);
191 setPromoteTo(ISD::VECTOR_SHUFFLE, T, ByteW);
|
| HexagonISelLowering.cpp | 1649 ISD::CONCAT_VECTORS, ISD::VECTOR_SHUFFLE,
1751 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i8, Custom);
1752 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
1753 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
3143 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
|
| HexagonISelDAGToDAG.cpp | 910 case ISD::VECTOR_SHUFFLE: return SelectHvxShuffle(N);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| WebAssemblyISelLowering.cpp | 146 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
177 setOperationAction(ISD::VECTOR_SHUFFLE, T, Custom);
1254 case ISD::VECTOR_SHUFFLE:
2240 case ISD::VECTOR_SHUFFLE:
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 765 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
766 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
841 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
871 // Custom lowering ROTL v1i128 to VECTOR_SHUFFLE v16i8.
994 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
1042 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
1328 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
2088 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
8886 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
9367 /// lowerToVINSERTB - Return the SDValue if this VECTOR_SHUFFLE can be handle
[all...] |
| PPCISelDAGToDAG.cpp | 5499 case ISD::VECTOR_SHUFFLE:
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| SIISelLowering.cpp | 334 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i32, Expand);
335 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Expand);
336 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i32, Expand);
337 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16f32, Expand);
693 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f16, Custom);
694 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
4510 case ISD::VECTOR_SHUFFLE:
5485 // XXX - Why doesn't this get called when vector_shuffle is expanded?
5524 // vector_shuffle <0,1,6,7> lhs, rhs
5527 // vector_shuffle <6,7,2,3> lhs, rh
[all...] |
| AMDGPUISelLowering.cpp | 452 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
488 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 352 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
645 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
4649 else if (Op.getOpcode() == ISD::VECTOR_SHUFFLE && Op.hasOneUse()) {
4941 // Represent the BUILD_VECTOR as an N-operand VECTOR_SHUFFLE-like operation
5467 case ISD::VECTOR_SHUFFLE:
5738 else if ((Opcode == ISD::VECTOR_SHUFFLE || Opcode == SystemZISD::SPLAT) &&
6083 Op1.getOpcode() == ISD::VECTOR_SHUFFLE &&
6125 // First, combine the VECTOR_SHUFFLE away. This makes the value produced
6711 case ISD::VECTOR_SHUFFLE: return combineVECTOR_SHUFFLE(N, DCI);
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | 1803 case ShuffleVector: return ISD::VECTOR_SHUFFLE;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 351 setOperationAction(ISD::VECTOR_SHUFFLE, Ty, Custom);
467 case ISD::VECTOR_SHUFFLE: return lowerVECTOR_SHUFFLE(Op, DAG);
2188 // We can't lower via VECTOR_SHUFFLE because it requires constant shuffle
2535 // Lower VECTOR_SHUFFLE into SHF (if possible).
2626 // Determine whether VECTOR_SHUFFLE is a SPLATI.
2651 // Lower VECTOR_SHUFFLE into ILVEV (if possible).
2697 // Lower VECTOR_SHUFFLE into ILVOD (if possible).
2743 // Lower VECTOR_SHUFFLE into ILVR (if possible).
2790 // Lower VECTOR_SHUFFLE into ILVL (if possible).
2839 // Lower VECTOR_SHUFFLE into PCKEV (if possible)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 892 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
990 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
997 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1417 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1502 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1730 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1875 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
2005 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
3899 /// Returns a vector_shuffle mask for an movs{s|d}, movd
6451 /// Returns a vector_shuffle node for an unpackl operation
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 375 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f16, Expand);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVISelLowering.cpp | 673 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
749 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1299 // The state of RVV BUILD_VECTOR and VECTOR_SHUFFLE lowering is that very few
1301 // where we try to lower a BUILD_VECTOR as a VECTOR_SHUFFLE as a BUILD_VECTOR
2314 case ISD::VECTOR_SHUFFLE:
|
