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    Searched refs:VEX (Results 1 - 10 of 10) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86InstrFMA3Info.cpp 133 bool IsFMA3 = ((TSFlags & X86II::EncodingMask) == X86II::VEX ||
X86MCInstLower.cpp 532 // Commute operands to get a smaller encoding by using VEX.R instead of VEX.B
935 // Swap the operands if it will enable a 2 byte VEX encoding.
960 // able to commute the operands to get a 2 byte VEX prefix.
963 (TSFlags & X86II::EncodingMask) == X86II::VEX &&
2374 // Add a comment about EVEX-2-VEX compression for AVX-512 instrs that
2375 // are compressed from EVEX encoding to VEX encoding.
2378 OutStreamer->AddComment("EVEX TO VEX Compression ", false);
X86ISelDAGToDAG.cpp 1536 // Make sure the instruction has a VEX, XOP, or EVEX prefix. This covers
1539 if ((TSFlags & X86II::EncodingMask) != X86II::VEX &&
  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
X86RecognizableInstr.h 141 VEX = 1, XOP = 2, EVEX = 3
188 /// Inferred from the operands; indicates whether the L bit in the VEX prefix is set
X86FoldTablesEmitter.cpp 313 // Function object - Operator() returns true if the given VEX instruction
331 // VEX/EVEX fields
503 } else if (Enc != X86Local::XOP && Enc != X86Local::VEX &&
505 // Instructions with VEX encoding do not require alignment.
X86RecognizableInstr.cpp 128 // Special case since there is no attribute class for 64-bit and VEX
163 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n";
164 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled");
252 } else if (Encoding == X86Local::VEX || Encoding == X86Local::XOP) {
506 // - In AVX, there is a register operand in the VEX.vvvv field here -
518 // in ModRMVEX and the one above the one in the VEX.VVVV field
528 // - In AVX, there is a register operand in the VEX.vvvv field here -
541 // in ModRMVEX and the one above the one in the VEX.VVVV field
550 // - In AVX, there is a register operand in the VEX.vvvv field here -
565 // in ModRMVEX and the one above the one in the VEX.VVVV fiel
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/
X86MCCodeEmitter.cpp 756 /// AVX instructions are encoded using a opcode prefix called VEX.
762 assert(!(TSFlags & X86II::LOCK) && "Can't have LOCK VEX.");
796 // VEX_5M (VEX m-mmmmm field):
830 // VEX_4V (VEX vvvv field): a register specifier
1141 if (Encoding == X86II::VEX || Encoding == X86II::XOP) {
1142 // VEX opcode prefix can have 2 or 3 bytes
1159 // Can we use the 2 byte VEX prefix?
1160 if (!(MI.getFlags() & X86::IP_USE_VEX3) && Encoding == X86II::VEX &&
1167 // 3 byte VEX prefix
1179 "More than 2 significant bits in VEX.m-mmmm fields for EVEX!")
    [all...]
X86BaseInfo.h 653 /// operand 3 with VEX.VVVV and load from memory.
693 /// operand 3 with VEX.VVVV and do not load from memory.
811 // XOPA - Prefix to encode 0xA in VEX.MMMM of XOP instructions.
898 // VEX - encoding using 0xC4/0xC5
899 VEX = 1 << EncodingShift,
924 /// VEX_L - Stands for a bit in the VEX opcode prefix meaning the current
959 // Force VEX encoding
X86MCTargetDesc.cpp 424 bool HasVEX = (Desc.TSFlags & X86II::EncodingMask) == X86II::VEX;
440 // Early exit if this instruction has no vex/evex/xop prefix.
444 // All VEX and EVEX encoded instructions are defined to zero the high bits
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/AsmParser/
X86AsmParser.cpp 3026 // Reset the forced VEX encoding.
3041 if (Prefix == "vex")
3071 if (Name.equals_lower("vex"))
3603 // We can get a smaller encoding by using VEX.R instead of VEX.B if one of
3632 // We can get a smaller encoding by using VEX.R instead of VEX.B if one of
3865 // check this with the legacy encoding, VEX/EVEX/XOP don't use REX.
4085 (MCID.TSFlags & X86II::EncodingMask) != X86II::VEX)
4088 // These instructions are only available with {vex}, {vex2} or {vex3} prefi
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