HomeSort by: relevance | last modified time | path
    Searched refs:VGPR (Results 1 - 6 of 6) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIMachineFunctionInfo.h 442 Register VGPR;
446 SpilledReg(Register R, int L) : VGPR (R), Lane (L) {}
449 bool hasReg() { return VGPR != 0;}
453 // VGPR used for SGPR spills
454 Register VGPR;
456 // If the VGPR is is used for SGPR spills in a non-entrypoint function, the
460 SGPRSpillVGPR(Register V, Optional<int> F) : VGPR(V), FI(F) {}
468 // Map WWM VGPR to a stack slot that is used to save/restore it in the
473 // Track VGPR + wave index for each subregister of the SGPR spilled to
481 // AGPRs used for VGPR spills
    [all...]
SIFrameLowering.cpp 66 // 1: If there is already a VGPR with free lanes, use it. We
67 // may already have to pay the penalty for spilling a CSR VGPR.
79 << printReg(Spill.VGPR, TRI) << ':' << Spill.Lane
94 // so we're forced to spill another VGPR to use for the spill.
100 << printReg(Spill.VGPR, TRI) << ':' << Spill.Lane << '\n';);
715 // A StackID of SGPRSpill implies that this is a spill from SGPR to VGPR.
756 // VGPRs used for SGPR->VGPR spills
766 buildPrologSpill(ST, TRI, *FuncInfo, LiveRegs, MF, MBB, MBBI, Reg.VGPR,
772 auto VGPR = Reg.first;
781 buildPrologSpill(ST, TRI, *FuncInfo, LiveRegs, MF, MBB, MBBI, VGPR, *FI)
    [all...]
SIMachineFunctionInfo.cpp 271 /// Reserve a slice of a VGPR to support spilling for FrameIndex \p FI.
302 // Reserve a VGPR (when NumVGPRSpillLanes = 0, WaveSize, 2*WaveSize, ..) and
304 // 1. One reserved VGPR being tracked by VGPRReservedForSGPRSpill is not yet
306 // 2. All spill lanes of reserved VGPR(s) are full and another spill lane is
309 assert(FuncInfo->VGPRReservedForSGPRSpill == SpillVGPRs.back().VGPR);
335 LaneVGPR = SpillVGPRs.back().VGPR;
344 /// Reserve a VGPR for spilling of SGPRs
360 /// Either AGPR is spilled to VGPR to vice versa.
614 // Remove VGPR which was reserved for SGPR spills if there are no spilled SGPRs
618 if (i->VGPR == ReservedVGPR)
    [all...]
SILowerSGPRSpills.cpp 35 "amdgpu-spill-vgpr-to-agpr",
248 // Find lowest available VGPR and use it as VGPR reserved for SGPR spills.
253 // Early out if pre-reservation of a VGPR for SGPR spilling is disabled.
267 // Note Non-CSR VGPR also need this as we may overwrite inactive lanes.
274 return SpillRegInfo.VGPR == PreReservedVGPR;
284 assert(LowestAvailableVGPR.isValid() && "Did not find an available VGPR");
314 // Free the reserved VGPR for later possible use by frame lowering.
354 // Try to eliminate stack used by VGPR spills before frame
384 assert(Spilled && "failed to spill SGPR to VGPR when allocated")
    [all...]
SIPeepholeSDWA.cpp 1182 Register VGPR = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1184 TII->get(AMDGPU::V_MOV_B32_e32), VGPR);
1190 Op.ChangeToRegister(VGPR, false);
SIRegisterInfo.cpp 31 "amdgpu-spill-sgpr-to-vgpr",
49 // This is mostly to spill SGPRs to memory. Spilling SGPRs into VGPR lanes emits
52 // When spilling to memory, the SGPRs are written into VGPR lanes and the VGPR
54 // For this, a VGPR is required where the needed lanes can be clobbered. The
55 // RegScavenger can provide a VGPR where currently active lanes can be
59 // - Try to scavenge VGPR
86 // The SGPRs are written into this VGPR, which is then written to scratch
145 // Tries to scavenge SGPRs to save EXEC and a VGPR. Uses v0 if no VGPR i
    [all...]

Completed in 51 milliseconds