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Searched refs:VIA_PCI_DMA_CSR0 (Results 1 - 3 of 3) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/via/
via_dmablit.h	`131 #define VIA_PCI_DMA_CSR0 0xE90 /* Command/Status Register of Channel 0 */`
via_dmablit.c	260 via_write(dev_priv, VIA_PCI_DMA_CSR0 + engine0x04, VIA_DMA_CSR_DD \| VIA_DMA_CSR_TD \| 266 via_write(dev_priv, VIA_PCI_DMA_CSR0 + engine0x04, VIA_DMA_CSR_DE \| VIA_DMA_CSR_TS); 267 via_read(dev_priv, VIA_PCI_DMA_CSR0 + engine0x04); 437 via_write(dev_priv, VIA_PCI_DMA_CSR0 + engine0x04, VIA_DMA_CSR_TA); 445 via_write(dev_priv, VIA_PCI_DMA_CSR0 + engine0x04, VIA_DMA_CSR_TD \| VIA_DMA_CSR_DD); 476 ((status = via_read(dev_priv, VIA_PCI_DMA_CSR0 + engine0x04)) & VIA_DMA_CSR_TD); 500 via_write(dev_priv, VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_TD);
via_irq.c	`80 {VIA_IRQ_DMA0_TD_ENABLE, VIA_IRQ_DMA0_TD_PENDING, VIA_PCI_DMA_CSR0, 89 {VIA_IRQ_DMA0_TD_ENABLE, VIA_IRQ_DMA0_TD_PENDING, VIA_PCI_DMA_CSR0,`

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