Searched refs:VI_VICLK_SEL_27MHZ (Results 1 - 2 of 2) sorted by relevance

/src/sys/arch/evbppc/nintendo/dev/
H A Dvireg.h162 #define VI_VICLK_SEL_27MHZ 0 macro
H A Dwiifb.c804 interlaced ? VI_VICLK_SEL_27MHZ : VI_VICLK_SEL_54MHZ);

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