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Searched refs:VM_CONTEXT0_CNTL (Results 1 - 17 of 17) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfxhub_v1_0.c	`189 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 190 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 191 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, 388 hub->vm_context0_cntl =`
amdgpu_mmhub_v1_0.c	`208 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 209 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 210 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, 430 hub->vm_context0_cntl =`
amdgpu_gmc_v7_0.c	`674 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 675 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 676 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);`
amdgpu_gmc_v8_0.c	`911 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 912 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 913 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);`
sid.h	`396 #define VM_CONTEXT0_CNTL 0x504`
/src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_rv770.c	`937 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT \| PAGE_TABLE_DEPTH(0) \| 942 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 959 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 1010 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);`
rv770d.h	`636 #define VM_CONTEXT0_CNTL 0x1410`
radeon_ni.c	`1318 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT \| PAGE_TABLE_DEPTH(0) \| 1375 WREG32(VM_CONTEXT0_CNTL, 0);`
nid.h	`129 #define VM_CONTEXT0_CNTL 0x1410`
radeon_r600.c	`1205 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT \| PAGE_TABLE_DEPTH(0) \| 1210 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 1227 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 1293 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);`
cikd.h	`512 #define VM_CONTEXT0_CNTL 0x1410`
sid.h	`394 #define VM_CONTEXT0_CNTL 0x1410`
radeon_evergreen.c	`2446 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT \| PAGE_TABLE_DEPTH(0) \| 2465 WREG32(VM_CONTEXT0_CNTL, 0); 2515 WREG32(VM_CONTEXT0_CNTL, 0);`
evergreend.h	`1138 #define VM_CONTEXT0_CNTL 0x1410`
r600d.h	`575 #define VM_CONTEXT0_CNTL 0x1410`
radeon_si.c	`4329 WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT \| PAGE_TABLE_DEPTH(0) \| 4394 WREG32(VM_CONTEXT0_CNTL, 0);`
radeon_cik.c	`5483 WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT \| PAGE_TABLE_DEPTH(0) \| 5577 WREG32(VM_CONTEXT0_CNTL, 0);`

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