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    Searched refs:VR4122_MDSIUINT_REG_W (Results 1 - 2 of 2) sorted by relevancy

/src/sys/arch/hpcmips/vr/
vr4122ip.c	75 VR4122_DSIUINT_REG_W,VR4122_MDSIUINT_REG_W },
icureg.h	199 #define VR4122_MDSIUINT_REG_W 0x016 /* Level2 Mask DSIU intr reg */ 209 #define MDSIUINT_REG_W VR4122_MDSIUINT_REG_W

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