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    Searched refs:VRC (Results 1 - 6 of 6) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
MachineSSAUpdater.h 43 /// VRC - Register class of the current virtual register.
44 const TargetRegisterClass *VRC;
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
MachineSSAUpdater.cpp 60 VRC = RC;
157 VRC, MRI, TII);
191 Loc, VRC, MRI, TII);
295 Updater->VRC, Updater->MRI,
306 Updater->VRC, Updater->MRI,
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIRegisterInfo.cpp 2085 const TargetRegisterClass *VRC = getVGPRClassForBitWidth(Size);
2086 if (!VRC) {
2090 return getCommonSubClass(VRC, RC) != nullptr;
2108 const TargetRegisterClass *VRC = getVGPRClassForBitWidth(Size);
2109 assert(VRC && "Invalid register class size");
2110 return VRC;
2122 SIRegisterInfo::getEquivalentSGPRClass(const TargetRegisterClass *VRC) const {
2123 unsigned Size = getRegSizeInBits(*VRC);
SIRegisterInfo.h 191 getEquivalentSGPRClass(const TargetRegisterClass *VRC) const;
SIInstrInfo.cpp 4516 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC);
4518 if (RI.getCommonSubClass(VRC64, VRC))
4519 VRC = VRC64;
4521 VRC = &AMDGPU::VGPR_32RegClass;
4523 Register Reg = MRI.createVirtualRegister(VRC);
4924 const TargetRegisterClass *VRC = MRI.getRegClass(SrcReg);
4925 const TargetRegisterClass *SRC = RI.getEquivalentSGPRClass(VRC);
4927 unsigned SubRegs = RI.getRegSizeInBits(*VRC) / 32;
4929 if (RI.hasAGPRs(VRC)) {
4930 VRC = RI.getEquivalentVGPRClass(VRC)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
InstrEmitter.cpp 450 const TargetRegisterClass *VRC = MRI->getRegClass(VReg);
451 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx);
453 // RC is a sub-class of VRC that supports SubIdx. Try to constrain VReg
455 if (RC && RC != VRC)

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