| /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| WebAssemblyRegNumbering.cpp | 79 LLVM_DEBUG(dbgs() << "Arg VReg " << MI.getOperand(0).getReg()
92 unsigned VReg = Register::index2VirtReg(VRegIdx);
94 if (MRI.use_empty(VReg))
97 if (MFI.isVRegStackified(VReg)) {
98 LLVM_DEBUG(dbgs() << "VReg " << VReg << " -> WAReg "
100 MFI.setWAReg(VReg, INT32_MIN | NumStackRegs++);
103 if (MFI.getWAReg(VReg) == WebAssemblyFunctionInfo::UnusedReg) {
104 LLVM_DEBUG(dbgs() << "VReg " << VReg << " -> WAReg " << CurReg << "\n")
[all...] |
| WebAssemblyReplacePhysRegs.cpp | 87 unsigned VReg = WebAssembly::NoRegister;
91 if (VReg == WebAssembly::NoRegister) {
92 VReg = MRI.createVirtualRegister(RC);
96 FI->setFrameBaseVreg(VReg);
98 dbgs() << "replacing preg " << PReg << " with " << VReg << " ("
99 << Register::virtReg2Index(VReg) << ")\n";
103 MO.setReg(VReg);
|
| WebAssemblyMachineFunctionInfo.h | 40 /// A mapping from CodeGen vreg index to WebAssembly register number.
43 /// A mapping from CodeGen vreg index to a boolean value indicating whether
60 // after it has been replaced by a vreg
98 assert(VarargVreg != -1U && "Vararg vreg hasn't been set");
104 assert(BasePtrVreg != -1U && "Base ptr vreg hasn't been set");
109 assert(FrameBaseVreg != -1U && "Frame base vreg hasn't been set");
124 void stackifyVReg(MachineRegisterInfo &MRI, unsigned VReg) {
125 assert(MRI.getUniqueVRegDef(VReg));
126 auto I = Register::virtReg2Index(VReg);
131 void unstackifyVReg(unsigned VReg) {
[all...] |
| WebAssemblyRegColoring.cpp | 64 // Compute the total spill weight for VReg.
67 unsigned VReg) {
69 for (MachineOperand &MO : MRI->reg_nodbg_operands(VReg))
101 unsigned VReg = Register::index2VirtReg(I);
102 if (MFI.isVRegStackified(VReg))
105 if (MRI->use_empty(VReg))
108 LiveInterval *LI = &Liveness->getInterval(VReg);
110 LI->setWeight(computeWeight(MRI, MBFI, VReg));
163 LLVM_DEBUG(dbgs() << "Assigning vreg" << Register::virtReg2Index(LI->reg())
164 << " to vreg" << Register::virtReg2Index(New) << "\n")
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/aarch64/ |
| cpustate.h | 90 typedef enum VReg
124 } VReg;
286 extern float aarch64_get_FP_half (sim_cpu *, VReg);
287 extern float aarch64_get_FP_float (sim_cpu *, VReg);
288 extern double aarch64_get_FP_double (sim_cpu *, VReg);
289 extern void aarch64_get_FP_long_double (sim_cpu *, VReg, FRegister *);
291 extern void aarch64_set_FP_half (sim_cpu *, VReg, float);
292 extern void aarch64_set_FP_float (sim_cpu *, VReg, float);
293 extern void aarch64_set_FP_double (sim_cpu *, VReg, double);
294 extern void aarch64_set_FP_long_double (sim_cpu *, VReg, FRegister)
[all...] |
| cpustate.c | 350 aarch64_get_FP_half (sim_cpu *cpu, VReg reg)
366 aarch64_get_FP_float (sim_cpu *cpu, VReg reg)
372 aarch64_get_FP_double (sim_cpu *cpu, VReg reg)
378 aarch64_get_FP_long_double (sim_cpu *cpu, VReg reg, FRegister *a)
387 aarch64_set_FP_half (sim_cpu *cpu, VReg reg, float val)
403 aarch64_set_FP_float (sim_cpu *cpu, VReg reg, float val)
423 aarch64_set_FP_double (sim_cpu *cpu, VReg reg, double val)
442 aarch64_set_FP_long_double (sim_cpu *cpu, VReg reg, FRegister a)
477 aarch64_get_vec_u64 (sim_cpu *cpu, VReg reg, unsigned element)
483 aarch64_get_vec_u32 (sim_cpu *cpu, VReg reg, unsigned element
[all...] |
| /src/external/gpl3/gdb/dist/sim/aarch64/ |
| cpustate.h | 90 typedef enum VReg
124 } VReg;
286 extern float aarch64_get_FP_half (sim_cpu *, VReg);
287 extern float aarch64_get_FP_float (sim_cpu *, VReg);
288 extern double aarch64_get_FP_double (sim_cpu *, VReg);
289 extern void aarch64_get_FP_long_double (sim_cpu *, VReg, FRegister *);
291 extern void aarch64_set_FP_half (sim_cpu *, VReg, float);
292 extern void aarch64_set_FP_float (sim_cpu *, VReg, float);
293 extern void aarch64_set_FP_double (sim_cpu *, VReg, double);
294 extern void aarch64_set_FP_long_double (sim_cpu *, VReg, FRegister)
[all...] |
| cpustate.c | 350 aarch64_get_FP_half (sim_cpu *cpu, VReg reg)
366 aarch64_get_FP_float (sim_cpu *cpu, VReg reg)
372 aarch64_get_FP_double (sim_cpu *cpu, VReg reg)
378 aarch64_get_FP_long_double (sim_cpu *cpu, VReg reg, FRegister *a)
387 aarch64_set_FP_half (sim_cpu *cpu, VReg reg, float val)
403 aarch64_set_FP_float (sim_cpu *cpu, VReg reg, float val)
423 aarch64_set_FP_double (sim_cpu *cpu, VReg reg, double val)
442 aarch64_set_FP_long_double (sim_cpu *cpu, VReg reg, FRegister a)
477 aarch64_get_vec_u64 (sim_cpu *cpu, VReg reg, unsigned element)
483 aarch64_get_vec_u32 (sim_cpu *cpu, VReg reg, unsigned element
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| SwiftErrorValueTracking.cpp | 37 auto VReg = MF->getRegInfo().createVirtualRegister(RC);
38 VRegDefMap[Key] = VReg;
39 VRegUpwardsUse[Key] = VReg;
40 return VReg;
46 const Value *Val, Register VReg) {
47 VRegDefMap[std::make_pair(MBB, Val)] = VReg;
59 Register VReg = MF->getRegInfo().createVirtualRegister(RC);
60 VRegDefUses[Key] = VReg;
61 setCurrentVReg(MBB, Val, VReg);
62 return VReg;
[all...] |
| MIRVRegNamerUtils.cpp | 1 //===---------- MIRVRegNamerUtils.cpp - MIR VReg Renaming Utilities -------===//
20 UseStableNamerHash("mir-vreg-namer-use-stable-hash", cl::init(false),
22 cl::desc("Use Stable Hashing for MIR VReg Renaming"));
50 for (const auto &VReg : VRegs) {
51 const unsigned Reg = VReg.getReg();
52 VRM[Reg] = createVirtualRegisterWithLowerName(Reg, GetUniqueVRegName(VReg));
139 unsigned VRegRenamer::createVirtualRegister(unsigned VReg) {
140 assert(Register::isVirtualRegister(VReg) && "Expected Virtual Registers");
141 std::string Name = getInstructionOpcodeHash(*MRI.getVRegDef(VReg));
142 return createVirtualRegisterWithLowerName(VReg, Name)
[all...] |
| LiveRangeEdit.cpp | 35 Register VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
37 VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg));
39 LiveInterval &LI = LIS.createEmptyInterval(VReg);
55 Register VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
57 VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg));
66 LIS.getInterval(VReg).markNotSpillable();
67 return VReg;
411 unsigned VReg = LI->reg();
413 TheDelegate->LRE_WillShrinkVirtReg(VReg);
423 if (VReg == RegsBeingSpilled[i])
[all...] |
| MIRVRegNamerUtils.h | 2 //===------------ MIRVRegNamerUtils.h - MIR VReg Renaming Utilities -------===//
55 /// the instruction defining that vreg.
67 /// Perform replacing of registers based on the <old,new> vreg map.
70 /// createVirtualRegister - Given an existing vreg, create a named vreg to
73 unsigned createVirtualRegister(unsigned VReg);
75 /// Create a vreg with name and return it.
76 unsigned createVirtualRegisterWithLowerName(unsigned VReg, StringRef Name);
79 /// vreg definition based on the semantics of the instruction.
88 /// will be used as prefix for the vreg names
[all...] |
| LiveIntervalUnion.cpp | 160 LiveInterval *VReg = LiveUnionI.value();
161 if (VReg != RecentReg && !isSeenInterference(VReg)) {
162 RecentReg = VReg;
163 InterferingVRegs->push_back(VReg);
|
| RegAllocPBQP.cpp | 161 /// Finds the initial set of vreg intervals to allocate.
167 /// Spill the given VReg.
168 void spillVReg(Register VReg, SmallVectorImpl<Register> &NewIntervals,
333 Register VReg = G.getNodeMetadata(NId).getVReg();
334 LiveInterval &LI = LIS.getInterval(VReg);
604 Register VReg = Worklist.back();
607 LiveInterval &VRegLI = LIS.getInterval(VReg);
617 const TargetRegisterClass *TRC = MRI.getRegClass(VReg);
623 // Compute an initial allowed set for the current vreg.
654 spillVReg(VReg, NewVRegs, MF, LIS, VRM, VRegSpiller)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCMachineFunctionInfo.cpp | 54 bool PPCFunctionInfo::isLiveInSExt(Register VReg) const {
56 if (LiveIn.first == VReg)
61 bool PPCFunctionInfo::isLiveInZExt(Register VReg) const {
63 if (LiveIn.first == VReg)
|
| PPCMachineFunctionInfo.h | 238 void addLiveInAttr(Register VReg, ISD::ArgFlagsTy Flags) {
239 LiveInAttrs.push_back(std::make_pair(VReg, Flags));
242 /// This function returns true if the specified vreg is
244 bool isLiveInSExt(Register VReg) const;
246 /// This function returns true if the specified vreg is
248 bool isLiveInZExt(Register VReg) const;
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| MachineRegisterInfo.h | 50 /// registers, including vreg register classes, use/def chains for registers,
72 /// Each element in this list contains the register class of the vreg and the
78 /// Map for recovering vreg name from vreg number.
82 /// StringSet that is used to unique vreg names.
217 bool shouldTrackSubRegLiveness(Register VReg) const {
218 assert(VReg.isVirtual() && "Must pass a VReg");
219 return shouldTrackSubRegLiveness(*getRegClass(VReg));
728 Register cloneVirtualRegister(Register VReg, StringRef Name = "")
[all...] |
| RegAllocPBQP.h | 93 /// Holds a vector of the allowed physical regs for a vreg.
148 void setNodeIdForVReg(Register VReg, GraphBase::NodeId NId) {
149 VRegToNodeId[VReg.id()] = NId;
152 GraphBase::NodeId getNodeIdForVReg(Register VReg) const {
153 auto VRegItr = VRegToNodeId.find(VReg);
187 OptUnsafeEdges(new unsigned[NumOpts]), VReg(Other.VReg),
202 void setVReg(Register VReg) { this->VReg = VReg; }
[all...] |
| ScheduleDAGInstrs.h | 57 VReg2SUnit(unsigned VReg, LaneBitmask LaneMask, SUnit *SU)
58 : VirtReg(VReg), LaneMask(LaneMask), SU(SU) {}
69 VReg2SUnitOperIdx(unsigned VReg, LaneBitmask LaneMask,
71 : VReg2SUnit(VReg, LaneMask, SU), OperandIndex(OperandIndex) {}
100 /// vreg use list.
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| InstructionSelect.cpp | 238 // that the size of the now-constrained vreg is unchanged and that it has a
241 unsigned VReg = Register::index2VirtReg(I);
244 if (!MRI.def_empty(VReg))
245 MI = &*MRI.def_instr_begin(VReg);
246 else if (!MRI.use_empty(VReg))
247 MI = &*MRI.use_instr_begin(VReg);
251 const TargetRegisterClass *RC = MRI.getRegClassOrNull(VReg);
254 "VReg has no regclass after selection", *MI);
258 const LLT Ty = MRI.getType(VReg);
262 "VReg's low-level type and register class have different sizes", *MI)
[all...] |
| Utils.cpp | 164 // If the operand is a vreg, we should constrain its regclass, and only
270 Optional<APInt> llvm::getConstantVRegVal(Register VReg,
273 getConstantVRegValWithLookThrough(VReg, MRI, /*LookThroughInstrs*/ false);
274 assert((!ValAndVReg || ValAndVReg->VReg == VReg) &&
281 Optional<int64_t> llvm::getConstantVRegSExtVal(Register VReg,
283 Optional<APInt> Val = getConstantVRegVal(VReg, MRI);
290 Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs,
315 while ((MI = MRI.getVRegDef(VReg)) && !IsConstantOpcode(MI->getOpcode()) &&
328 VReg = MI->getOperand(1).getReg()
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/ |
| Utils.h | 164 /// If \p VReg is defined by a G_CONSTANT, return the corresponding value.
165 Optional<APInt> getConstantVRegVal(Register VReg,
168 /// If \p VReg is defined by a G_CONSTANT fits in int64_t
170 Optional<int64_t> getConstantVRegSExtVal(Register VReg,
177 Register VReg;
179 /// If \p VReg is defined by a statically evaluable chain of
189 getConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI,
193 const ConstantInt *getConstantIntVRegVal(Register VReg,
195 const ConstantFP* getConstantFPVRegVal(Register VReg,
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| SDNodeDbgValue.h | 36 VREG = 3 ///< Value is a virtual register.
64 /// Returns the Virtual Register for a VReg
66 assert(kind == VREG);
67 return u.VReg;
76 static SDDbgOperand fromVReg(unsigned VReg) {
77 return SDDbgOperand(VReg, VREG);
92 case VREG:
109 unsigned VReg; ///< Valid for registers.
121 assert((Kind == VREG || Kind == FRAMEIX) &
[all...] |
| InstrEmitter.cpp | 103 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
104 // the CopyToReg'd destination register instead of creating a new vreg.
208 // is a vreg in the same register class, use the CopyToReg'd destination
209 // register instead of creating a new vreg.
283 Register VReg = MRI->createVirtualRegister(RC);
285 TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
286 return VReg;
309 Register VReg = getVR(Op, VRBaseMap);
317 // shrink VReg's register class within reason. For example, if VReg == GR3
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/MIRParser/ |
| MIRParser.cpp | 552 for (const auto &VReg : YamlMF.VirtualRegisters) {
553 VRegInfo &Info = PFS.getVRegInfo(VReg.ID.Value);
555 return error(VReg.ID.SourceRange.Start,
557 Twine(VReg.ID.Value) + "'");
560 if (StringRef(VReg.Class.Value).equals("_")) {
564 const auto *RC = Target->getRegClass(VReg.Class.Value);
569 const RegisterBank *RegBank = Target->getRegBank(VReg.Class.Value);
572 VReg.Class.SourceRange.Start,
574 VReg.Class.Value + "'");
580 if (!VReg.PreferredRegister.Value.empty())
[all...] |
