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    Searched refs:VReg2 (Results 1 - 3 of 3) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMInstructionSelector.cpp 250 Register VReg2 = MIB.getReg(2);
251 (void)VReg2;
252 assert(MRI.getType(VReg2).getSizeInBits() == 32 &&
253 RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::GPRRegBankID &&
282 Register VReg2 = MIB.getReg(2);
283 (void)VReg2;
284 assert(MRI.getType(VReg2).getSizeInBits() == 64 &&
285 RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::FPRRegBankID &&
ARMISelLowering.cpp 10304 unsigned VReg2 = VReg1;
10306 VReg2 = MRI->createVirtualRegister(TRC);
10307 BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVTi16), VReg2)
10315 .addReg(VReg2)
10441 unsigned VReg2 = VReg1;
10443 VReg2 = MRI->createVirtualRegister(TRC);
10444 BuildMI(DispatchBB, dl, TII->get(ARM::MOVTi16), VReg2)
10452 .addReg(VReg2)
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCInstrInfo.cpp 716 Register VReg2 = MRI->createVirtualRegister(RC);
723 BuildMI(*MF, MI->getDebugLoc(), get(LoadOpcode), VReg2)
733 return VReg2;

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