| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 675 /// At first, the VSELECT condition is of vXi1 type. Later, targets may
676 /// change the condition type in order to match the VSELECT node using a
678 VSELECT,
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| BasicTTIImpl.h | 1035 ISD = ISD::VSELECT;
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| SelectionDAG.h | 1074 auto Opcode = Cond.getValueType().isVector() ? ISD::VSELECT : ISD::SELECT;
1086 /// Try to simplify a select/vselect into 1 of its operands or a constant.
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| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 106 setTargetDAGCombine(ISD::VSELECT);
167 setTargetDAGCombine(ISD::VSELECT);
352 setOperationAction(ISD::VSELECT, Ty, Legal);
397 setOperationAction(ISD::VSELECT, Ty, Legal);
594 // - (or (and $a, $mask), (and $b, $inv_mask)) => (vselect $mask, $a, $b)
710 // Transform the DAG into an equivalent VSELECT.
711 return DAG.getNode(ISD::VSELECT, SDLoc(N), Ty, Cond, IfSet, IfClr);
1046 case ISD::VSELECT:
1611 // binsli_x(IfClear, IfSet, nbits) -> (vselect LBitsMask, IfSet, IfClear)
1618 return DAG.getNode(ISD::VSELECT, DL, VecTy
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonISelLoweringHVX.cpp | 184 setOperationAction(ISD::VSELECT, T, Custom);
270 setTargetDAGCombine(ISD::VSELECT);
1719 SDValue VSel = DAG.getNode(ISD::VSELECT, dl, ValTy, Mask, Load, Thru);
2088 case ISD::VSELECT:
2245 case ISD::VSELECT: {
2246 // (vselect (xor x, qtrue), v0, v1) -> (vselect x, v1, v0)
2251 return DAG.getNode(ISD::VSELECT, dl, ty(Op), C0, Ops[2], Ops[1]);
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| HexagonISelLowering.cpp | 1749 setOperationAction(ISD::VSELECT, MVT::v4i8, Custom);
1750 setOperationAction(ISD::VSELECT, MVT::v2i16, Custom);
1803 setTargetDAGCombine(ISD::VSELECT);
3169 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
3255 } else if (Opc == ISD::VSELECT) {
3258 // (vselect (xor x, ptrue), v0, v1) -> (vselect x, v1, v0)
3263 SDValue VSel = DCI.DAG.getNode(ISD::VSELECT, dl, ty(Op), C0,
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| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 133 /// Implement vselect in terms of XOR, AND, OR when blend is not
398 case ISD::VSELECT:
754 case ISD::VSELECT:
911 // operands are vectors. Lower this select to VSELECT and implement it
1168 // Implement VSELECT in terms of XOR, AND, OR
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| SelectionDAGDumper.cpp | 282 case ISD::VSELECT: return "vselect";
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| LegalizeVectorTypes.cpp | 61 case ISD::VSELECT: R = ScalarizeVecRes_VSELECT(N); break;
443 // The vselect result and true/value operands needs scalarizing, but it's
628 case ISD::VSELECT:
915 case ISD::VSELECT:
2178 case ISD::VSELECT:
2264 assert(Mask.getValueType().isVector() && "VSELECT without a vector mask?");
2281 DAG.getNode(ISD::VSELECT, DL, LoOpVT, LoMask, LoOp0, LoOp1);
2283 DAG.getNode(ISD::VSELECT, DL, HiOpVT, HiMask, HiOp0, HiOp1);
2992 case ISD::VSELECT:
4236 // This method tries to handle some special cases for the vselect mas
[all...] |
| TargetLowering.cpp | 2675 case ISD::VSELECT: {
2681 // TODO - add support for constant vselect masks (see IR version of this).
2687 // See if we can simplify either vselect operand.
5651 if (isOperationLegalOrCustom(ISD::VSELECT, SETCCVT)) {
5656 return DAG.getNode(ISD::VSELECT, DL, SETCCVT, TautologicalInvertedChannels,
5662 // NOTE: see the note above VSELECT above.
5915 !isOperationLegalOrCustom(ISD::VSELECT, VT))
5942 DAG.getNode(ISD::VSELECT, DL, VT, DivisorIsIntMin, MaskedIsZero, Fold);
7946 if (VT.isVector() && !isOperationLegalOrCustom(ISD::VSELECT, VT))
7997 if (VT.isVector() && !isOperationLegalOrCustom(ISD::VSELECT, VT)
[all...] |
| LegalizeIntegerTypes.cpp | 77 case ISD::VSELECT: Res = PromoteIntRes_VSELECT(N); break;
1048 return DAG.getNode(ISD::VSELECT, SDLoc(N),
1499 case ISD::VSELECT:
1758 if (N->getOpcode() == ISD::VSELECT)
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| SelectionDAG.cpp | 3055 case ISD::VSELECT:
3850 case ISD::VSELECT:
6030 case ISD::VSELECT:
7738 // TODO: This should simplify VSELECT with constant condition using something
9958 case ISD::VSELECT:
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| DAGCombiner.cpp | 1665 case ISD::VSELECT: return visitVSELECT(N);
9367 assert((N->getOpcode() == ISD::SELECT || N->getOpcode() == ISD::VSELECT) &&
9568 // This function assumes all the vselect's arguments are CONCAT_VECTOR
9587 // concat_vectors we have as arguments to vselect.
9818 // vselect <N x i1> Cond, C+1, C --> add (zext Cond), C
9819 // vselect <N x i1> Cond, C-1, C --> add (sext Cond), C
9838 // vselect <N x i1> Cond, C1, C2 --> xor (and (sext Cond), (C1^C2)), C2
9839 // ...but that only makes sense if a vselect is slower than 2 logic ops, so
9857 // vselect (not Cond), N1, N2 -> vselect Cond, N2, N
[all...] |
| SelectionDAGBuilder.cpp | 3256 Cond.getValueType().isVector() ? ISD::VSELECT : ISD::SELECT;
3276 // If the vselect is legal, assume we want to leave this as a vector setcc +
3277 // vselect. Otherwise, if this is going to be scalarized, we want to see if
3280 !TLI.isOperationLegalOrCustom(ISD::VSELECT, VT);
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| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 893 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
991 setOperationAction(ISD::VSELECT, VT, Custom);
998 setOperationAction(ISD::VSELECT, VT, Custom);
1151 // We directly match byte blends in the backend as they match the VSELECT
1153 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1418 setOperationAction(ISD::VSELECT, VT, Custom);
1428 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1488 setOperationAction(ISD::VSELECT, VT, Expand);
1727 setOperationAction(ISD::VSELECT, VT, Custom);
1868 setOperationAction(ISD::VSELECT, VT, Expand)
[all...] |
| X86ISelDAGToDAG.cpp | 722 (N->getOpcode() == ISD::VSELECT || N->getOpcode() == X86ISD::SELECTS) &&
966 case ISD::VSELECT: {
967 // Replace VSELECT with non-mask conditions with with BLENDV.
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| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 189 setOperationAction(ISD::VSELECT, VT, Expand);
450 setOperationAction(ISD::VSELECT, VT, Expand);
1521 setTargetDAGCombine(ISD::VSELECT);
8145 DAG.getNode(ISD::VSELECT, dl, MVT::v16i8, RecastV1, AllOnes, AllZeroes);
9642 Combo = DAG.getNode(ISD::VSELECT, dl, VT, Mask, NewLoad, PassThru);
12587 } else if (N->getOpcode() == ISD::VSELECT) {
12588 // Detect a SMIN, which for an i64 node will be a vselect/setcc, not a smin.
12660 // Transforms vselect(not(cond), lhs, rhs) into vselect(cond, rhs, lhs).
12682 // Rewrite into vselect(cond, rhs, lhs)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVISelLowering.cpp | 708 setOperationAction(ISD::VSELECT, VT, Custom);
777 setOperationAction(ISD::VSELECT, VT, Custom);
1589 // Blend in all instances of this value using a VSELECT, using a
1596 Vec = DAG.getNode(ISD::VSELECT, DL, VT,
1810 // Now construct the mask that will be used by the vselect or blended
1838 return DAG.getNode(ISD::VSELECT, DL, VT, SelectMask, V1, V2);
2402 case ISD::VSELECT:
2970 // Custom-lower extensions from mask vectors by using a vselect either with 1
2972 // (vXiN = (s|z)ext vXi1:vmask) -> (vXiN = vselect vmask, (-1 or 1), 0)
3004 return DAG.getNode(ISD::VSELECT, DL, VecVT, Src, SplatTrueVal, SplatZero)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 904 setTargetDAGCombine(ISD::VSELECT);
1391 setOperationAction(ISD::VSELECT, VT, Expand);
1525 setOperationAction(ISD::VSELECT, VT, Custom);
4697 case ISD::VSELECT:
7189 return DAG.getNode(ISD::VSELECT, DL, Ty, SplatPred, TVal, FVal);
7200 return DAG.getNode(ISD::VSELECT, DL, Ty, SplatPred, TVal, FVal);
14109 return DAG.getNode(ISD::VSELECT, SDLoc(N), N->getValueType(0),
15385 // vselect (v1i1 setcc) ->
15386 // vselect (v1iXX setcc) (XX is the size of the compared operand type)
15387 // FIXME: Currently the type legalizer can't handle VSELECT having v1i1 a
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelLowering.cpp | 445 setOperationAction(ISD::VSELECT, VT, Expand);
485 setOperationAction(ISD::VSELECT, VT, Expand);
2238 // compare and vselect end up producing worse code than scalarizing the whole
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| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 779 setOperationAction(ISD::VSELECT, VT, Legal);
1339 setTargetDAGCombine(ISD::VSELECT);
15380 case ISD::VSELECT:
16950 // from (vselect (setcc a, b, setugt), (sub a, b), (sub b, a)) to (vabsd a, b)
16951 // from (vselect (setcc a, b, setuge), (sub a, b), (sub b, a)) to (vabsd a, b)
16952 // from (vselect (setcc a, b, setult), (sub b, a), (sub a, b)) to (vabsd a, b)
16953 // from (vselect (setcc a, b, setule), (sub b, a), (sub a, b)) to (vabsd a, b)
16956 assert((N->getOpcode() == ISD::VSELECT) && "Need VSELECT node here");
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| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 345 setOperationAction(ISD::VSELECT, VT, Legal);
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