| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | 184 template<MVT::SimpleValueType VT>
186 return SelectSVEAddSubImm(N, VT, Imm, Shift);
189 template <MVT::SimpleValueType VT, bool Invert = false>
191 return SelectSVELogicalImm(N, VT, Imm, Invert);
194 template <MVT::SimpleValueType VT>
196 return SelectSVEArithImm(N, VT, Imm);
327 bool SelectSVEAddSubImm(SDValue N, MVT VT, SDValue &Imm, SDValue &Shift);
329 bool SelectSVELogicalImm(SDValue N, MVT VT, SDValue &Imm, bool Invert);
335 bool SelectSVEArithImm(SDValue N, MVT VT, SDValue &Imm);
1250 EVT VT = N->getValueType(0)
[all...] |
| AArch64ISelLowering.cpp | 129 static inline EVT getPackedSVEVectorVT(EVT VT) {
130 switch (VT.getSimpleVT().SimpleTy) {
169 static inline EVT getPromotedVTForPredicate(EVT VT) {
170 assert(VT.isScalableVector() && (VT.getVectorElementType() == MVT::i1) &&
172 switch (VT.getVectorMinNumElements()) {
186 /// Returns true if VT's elements occupy the lowest bit positions of its
191 static inline bool isPackedVectorType(EVT VT, SelectionDAG &DAG) {
192 assert(VT.isVector() && DAG.getTargetLoweringInfo().isTypeLegal(VT) &
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Support/ |
| LowLevelType.cpp | 18 LLT::LLT(MVT VT) {
19 if (VT.isVector()) {
20 init(/*IsPointer=*/false, VT.getVectorNumElements() > 1,
21 VT.getVectorNumElements(), VT.getVectorElementType().getSizeInBits(),
23 } else if (VT.isValid()) {
26 assert(VT.getSizeInBits().isNonZero() && "invalid zero-sized type");
28 VT.getSizeInBits(), /*AddressSpace=*/0);
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| ValueTypes.h | 45 bool operator==(EVT VT) const {
46 return !(*this != VT);
48 bool operator!=(EVT VT) const {
49 if (V.SimpleTy != VT.V.SimpleTy)
52 return LLVMTy != VT.LLVMTy;
73 /// each element is of type VT.
74 static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements,
76 MVT M = MVT::getVectorVT(VT.V, NumElements, IsScalable);
79 return getExtendedVectorVT(Context, VT, NumElements, IsScalable);
83 /// where each element is of type VT
[all...] |
| SelectionDAG.h | 103 SDVTListNode(const FoldingSetNodeIDRef ID, const EVT *VT, unsigned int Num) :
104 FastID(ID), VTs(VT), NumVTs(Num) {
602 SDVTList getVTList(EVT VT);
612 /// If VT is a vector type, the constant is splatted into a BUILD_VECTOR.
617 SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT,
619 SDValue getConstant(const APInt &Val, const SDLoc &DL, EVT VT,
622 SDValue getAllOnesConstant(const SDLoc &DL, EVT VT, bool IsTarget = false,
624 return getConstant(APInt::getAllOnesValue(VT.getScalarSizeInBits()), DL,
625 VT, IsTarget, IsOpaque);
628 SDValue getConstant(const ConstantInt &Val, const SDLoc &DL, EVT VT,
[all...] |
| TargetLowering.h | 432 getPreferredVectorAction(MVT VT) const {
434 if (VT.getVectorElementCount().isScalar())
437 if (!VT.isPow2VectorType())
459 shouldExpandBuildVectorWithShuffles(EVT /* VT */,
468 virtual bool isIntDivCheap(EVT VT, AttributeList Attr) const { return false; }
471 virtual bool hasStandaloneRem(EVT VT) const {
492 int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const;
498 int getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const;
504 int getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const;
510 int getDivRefinementSteps(EVT VT, MachineFunction &MF) const
[all...] |
| RuntimeLibcalls.h | 62 Libcall getSYNC(unsigned Opc, MVT VT);
66 Libcall getOUTLINE_ATOMIC(unsigned Opc, AtomicOrdering Order, MVT VT);
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| CallingConvLower.cpp | 95 MVT ArgVT = Ins[i].VT;
108 MVT VT = Outs[i].VT;
110 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this))
122 MVT VT = Outs[i].VT;
124 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this))
135 MVT ArgVT = Outs[i].VT;
[all...] |
| TargetLoweringBase.cpp | 473 MVT VT) {
475 switch (VT.SimpleTy) {
549 RTLIB::Libcall RTLIB::getSYNC(unsigned Opc, MVT VT) {
552 switch (VT.SimpleTy) { \
717 for (MVT VT : MVT::fp_valuetypes()) {
718 MVT IntVT = MVT::getIntegerVT(VT.getFixedSizeInBits());
720 setOperationAction(ISD::ATOMIC_SWAP, VT, Promote);
721 AddPromotedToType(ISD::ATOMIC_SWAP, VT, IntVT);
726 for (MVT VT : MVT::all_valuetypes()) {
730 setIndexedLoadAction(IM, VT, Expand)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| WebAssemblyMachineFunctionInfo.cpp | 41 for (EVT VT : VTs) {
42 unsigned NumRegs = TLI.getNumRegisters(F.getContext(), VT);
43 MVT RegisterVT = TLI.getRegisterType(F.getContext(), VT);
114 for (auto VT : MFI.getParams())
115 Params.push_back(EVT(VT).getEVTString());
116 for (auto VT : MFI.getResults())
117 Results.push_back(EVT(VT).getEVTString());
144 for (auto VT : YamlMFI.Params)
145 addParam(WebAssembly::parseMVT(VT.Value));
146 for (auto VT : YamlMFI.Results
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| DAGCombiner.cpp | 249 for (MVT VT : MVT::all_valuetypes())
250 if (EVT(VT).isSimple() && VT != MVT::Other &&
251 TLI.isTypeLegal(EVT(VT)) &&
252 VT.getSizeInBits().getKnownMinSize() >= MaximumLegalStoreInBits)
253 MaximumLegalStoreInBits = VT.getSizeInBits().getKnownMinSize();
554 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
564 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
761 /// given by \p Opcode for type \p VT, that is, whether the operation
764 bool hasOperation(unsigned Opcode, EVT VT) {
[all...] |
| LegalizeVectorOps.cpp | 603 MVT VT = Node->getSimpleValueType(0);
604 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
625 if ((VT.isFloatingPoint() && NVT.isFloatingPoint()) ||
626 (VT.isVector() && VT.getVectorElementType().isFloatingPoint() &&
628 Res = DAG.getNode(ISD::FP_ROUND, dl, VT, Res, DAG.getIntPtrConstant(0, dl));
630 Res = DAG.getNode(ISD::BITCAST, dl, VT, Res);
640 MVT VT = Node->getOperand(IsStrict ? 1 : 0).getSimpleValueType();
641 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
642 assert(NVT.getVectorNumElements() == VT.getVectorNumElements() &
[all...] |
| TargetLowering.cpp | 207 EVT VT = getOptimalMemOpType(Op, FuncAttributes);
209 if (VT == MVT::Other) {
213 VT = MVT::i64;
215 while (Op.getDstAlign() < (VT.getSizeInBits() / 8) &&
216 !allowsMisalignedMemoryAccesses(VT, DstAS, Op.getDstAlign()))
217 VT = (MVT::SimpleValueType)(VT.getSimpleVT().SimpleTy - 1);
218 assert(VT.isInteger());
228 if (VT.bitsGT(LVT))
229 VT = LVT
[all...] |
| SelectionDAG.cpp | 124 bool ConstantFPSDNode::isValueValidForType(EVT VT,
126 assert(VT.isFloatingPoint() && "Can only convert between FP types");
131 (void) Val2.convert(SelectionDAG::EVTToAPFloatSemantics(VT),
931 EVT VT = N->getValueType(0);
933 assert(!VT.isVector() && (VT.isInteger() || VT.isFloatingPoint()) &&
938 assert(N->getOperand(0).getValueType().isInteger() == VT.isInteger() &&
940 assert(VT.getSizeInBits() == 2 * N->getOperand(0).getValueSizeInBits() &&
1007 EVT VT = cast<VTSDNode>(N)->getVT()
[all...] |
| /src/external/bsd/byacc/dist/test/btyacc/ |
| ok_syntax1.tab.h | 20 #define VT 272
|
| /src/external/bsd/byacc/dist/test/yacc/ |
| ok_syntax1.tab.h | 17 #define VT 272
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 188 for (MVT VT : MVT::integer_valuetypes())
189 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
202 for (auto VT : {MVT::f32, MVT::f64, MVT::f80}) {
203 setCondCodeAction(ISD::SETOEQ, VT, Expand);
204 setCondCodeAction(ISD::SETUNE, VT, Expand);
300 for (MVT VT : { MVT::i8, MVT::i16, MVT::i32 }) {
301 setOperationAction(ISD::FP_TO_UINT_SAT, VT, Custom);
302 setOperationAction(ISD::FP_TO_SINT_SAT, VT, Custom);
336 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
337 setOperationAction(ISD::MULHS, VT, Expand)
[all...] |
| X86InterleavedAccess.cpp | 233 static MVT scaleVectorType(MVT VT) {
234 unsigned ScalarSize = VT.getVectorElementType().getScalarSizeInBits() * 2;
236 VT.getVectorNumElements() / 2);
261 static void genShuffleBland(MVT VT, ArrayRef<int> Mask,
264 assert(VT.getSizeInBits() >= 256 &&
266 unsigned NumOfElm = VT.getVectorNumElements();
291 static void reorderSubVector(MVT VT, SmallVectorImpl<Value *> &TransposedMatrix,
306 genShuffleBland(VT, VPShuf, OptimizeShuf, (i / Stride) * 16,
331 MVT VT = MVT::v8i16;
342 createUnpackShuffleMask(VT, MaskLowTemp1, true, false)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelLowering.cpp | 38 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) {
39 unsigned StoreSize = VT.getStoreSizeInBits();
48 EVT VT = Op.getValueType();
50 return VT.getSizeInBits() - Known.countMinLeadingZeros();
54 EVT VT = Op.getValueType();
58 return VT.getSizeInBits() - DAG.ComputeNumSignBits(Op);
122 for (MVT VT : MVT::integer_valuetypes()) {
123 setLoadExtAction(ISD::EXTLOAD, MVT::i64, VT, Expand);
124 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, VT, Expand);
125 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, VT, Expand)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsCallLowering.h | 39 unsigned ArgLocsStartIndex, const EVT &VT);
47 bool assign(Register VReg, const CCValAssign &VA, const EVT &VT);
53 const EVT &VT) = 0;
61 const EVT &VT) = 0;
|
| /src/external/bsd/ntp/dist/include/ |
| ascii.h | 54 #define VT 11
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/Support/ |
| VersionTuple.h | 148 friend llvm::hash_code hash_value(const VersionTuple &VT) {
149 return llvm::hash_combine(VT.Major, VT.Minor, VT.Subminor, VT.Build);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| AVRISelLowering.cpp | 59 for (MVT VT : MVT::integer_valuetypes()) {
61 setLoadExtAction(N, VT, MVT::i1, Promote);
62 setLoadExtAction(N, VT, MVT::i8, Expand);
68 for (MVT VT : MVT::integer_valuetypes()) {
69 setOperationAction(ISD::ADDC, VT, Legal);
70 setOperationAction(ISD::SUBC, VT, Legal);
71 setOperationAction(ISD::ADDE, VT, Legal);
72 setOperationAction(ISD::SUBE, VT, Legal);
134 for (MVT VT : MVT::integer_valuetypes()) {
135 setOperationAction(ISD::ATOMIC_SWAP, VT, Expand)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| BPFISelLowering.cpp | 84 for (auto VT : {MVT::i8, MVT::i16, MVT::i32}) {
85 if (VT == MVT::i32) {
89 setOperationAction(ISD::ATOMIC_LOAD_ADD, VT, Custom);
92 setOperationAction(ISD::ATOMIC_LOAD_AND, VT, Custom);
93 setOperationAction(ISD::ATOMIC_LOAD_OR, VT, Custom);
94 setOperationAction(ISD::ATOMIC_LOAD_XOR, VT, Custom);
95 setOperationAction(ISD::ATOMIC_SWAP, VT, Custom);
96 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
99 for (auto VT : { MVT::i32, MVT::i64 }) {
100 if (VT == MVT::i32 && !STI.getHasAlu32()
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVISelLowering.cpp | 111 auto addRegClassForRVV = [this](MVT VT) {
112 unsigned Size = VT.getSizeInBits().getKnownMinValue();
124 addRegisterClass(VT, RC);
127 for (MVT VT : BoolVecVTs)
128 addRegClassForRVV(VT);
129 for (MVT VT : IntVecVTs)
130 addRegClassForRVV(VT);
133 for (MVT VT : F16VecVTs)
134 addRegClassForRVV(VT);
137 for (MVT VT : F32VecVTs
[all...] |
