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    Searched refs:V_16 (Results 1 - 4 of 4) sorted by relevancy

/src/external/gpl3/gdb.old/dist/opcodes/
s390-opc.c	128 #define V_16 (V_CP16_12+1) /* Vector reg. starting at position 16 */ 130 #define V_32 (V_16 + 1) /* Vector reg. starting at position 32 */ 495 #define INSTR_VRI_VVV0UU 6, { V_8,V_12,V_16,U8_24,U4_32,0 } /* e.g. verim */ 496 #define INSTR_VRI_VVV0UU2 6, { V_8,V_12,V_16,U8_28,U4_24,0 } /* e.g. vap */ 497 #define INSTR_VRI_VVV0U 6, { V_8,V_12,V_16,U8_24,0,0 } /* e.g. verimb*/ 513 #define INSTR_VRR_VVV0U 6, { V_8,V_12,V_16,U4_32,0,0 } /* e.g. vmrh */ 514 #define INSTR_VRR_VVV0U0 6, { V_8,V_12,V_16,U4_24,0,0 } /* e.g. vfaeb */ 515 #define INSTR_VRR_VVV0U1 6, { V_8,V_12,V_16,U4_OR1_24,0,0 } /* e.g. vfaebs*/ 516 #define INSTR_VRR_VVV0U2 6, { V_8,V_12,V_16,U4_OR2_24,0,0 } /* e.g. vfaezb*/ 517 #define INSTR_VRR_VVV0U3 6, { V_8,V_12,V_16,U4_OR3_24,0,0 } /* e.g. vfaezbs*     [all...]
/src/external/gpl3/binutils/dist/opcodes/
s390-opc.c	130 #define V_16 (V_CP16_12+1) /* Vector reg. starting at position 16 */ 132 #define V_32 (V_16 + 1) /* Vector reg. starting at position 32 */ 486 #define INSTR_VRI_VVV0UU 6, { V_8,V_12,V_16,U8_24,U4_32,0 } /* e.g. verim */ 487 #define INSTR_VRI_VVV0UU2 6, { V_8,V_12,V_16,U8_28,U4_24,0 } /* e.g. vap */ 488 #define INSTR_VRI_VVV0U 6, { V_8,V_12,V_16,U8_24,0,0 } /* e.g. verimb*/ 493 #define INSTR_VRI_VVV0UV 6, { V_8,V_12,V_16,V_32,U8_24,0 } /* e.g. veval */ 505 #define INSTR_VRR_VVV0U 6, { V_8,V_12,V_16,U4_32,0,0 } /* e.g. vmrh */ 506 #define INSTR_VRR_VVV0U0 6, { V_8,V_12,V_16,U4_24,0,0 } /* e.g. vfaeb */ 507 #define INSTR_VRR_VVV0U02 6, { V_8,V_12,V_16,U4_28,0,0 } /* e.g. vd */ 511 #define INSTR_VRR_VVV 6, { V_8,V_12,V_16,0,0,0 } /* e.g. vmrhb *     [all...]
/src/external/gpl3/binutils.old/dist/opcodes/
s390-opc.c	130 #define V_16 (V_CP16_12+1) /* Vector reg. starting at position 16 */ 132 #define V_32 (V_16 + 1) /* Vector reg. starting at position 32 */ 486 #define INSTR_VRI_VVV0UU 6, { V_8,V_12,V_16,U8_24,U4_32,0 } /* e.g. verim */ 487 #define INSTR_VRI_VVV0UU2 6, { V_8,V_12,V_16,U8_28,U4_24,0 } /* e.g. vap */ 488 #define INSTR_VRI_VVV0U 6, { V_8,V_12,V_16,U8_24,0,0 } /* e.g. verimb*/ 493 #define INSTR_VRI_VVV0UV 6, { V_8,V_12,V_16,V_32,U8_24,0 } /* e.g. veval */ 505 #define INSTR_VRR_VVV0U 6, { V_8,V_12,V_16,U4_32,0,0 } /* e.g. vmrh */ 506 #define INSTR_VRR_VVV0U0 6, { V_8,V_12,V_16,U4_24,0,0 } /* e.g. vfaeb */ 507 #define INSTR_VRR_VVV0U02 6, { V_8,V_12,V_16,U4_28,0,0 } /* e.g. vd */ 511 #define INSTR_VRR_VVV 6, { V_8,V_12,V_16,0,0,0 } /* e.g. vmrhb *     [all...]
/src/external/gpl3/gdb/dist/opcodes/
s390-opc.c	130 #define V_16 (V_CP16_12+1) /* Vector reg. starting at position 16 */ 132 #define V_32 (V_16 + 1) /* Vector reg. starting at position 32 */ 486 #define INSTR_VRI_VVV0UU 6, { V_8,V_12,V_16,U8_24,U4_32,0 } /* e.g. verim */ 487 #define INSTR_VRI_VVV0UU2 6, { V_8,V_12,V_16,U8_28,U4_24,0 } /* e.g. vap */ 488 #define INSTR_VRI_VVV0U 6, { V_8,V_12,V_16,U8_24,0,0 } /* e.g. verimb*/ 493 #define INSTR_VRI_VVV0UV 6, { V_8,V_12,V_16,V_32,U8_24,0 } /* e.g. veval */ 505 #define INSTR_VRR_VVV0U 6, { V_8,V_12,V_16,U4_32,0,0 } /* e.g. vmrh */ 506 #define INSTR_VRR_VVV0U0 6, { V_8,V_12,V_16,U4_24,0,0 } /* e.g. vfaeb */ 507 #define INSTR_VRR_VVV0U02 6, { V_8,V_12,V_16,U4_28,0,0 } /* e.g. vd */ 511 #define INSTR_VRR_VVV 6, { V_8,V_12,V_16,0,0,0 } /* e.g. vmrhb *     [all...]

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Indexes created Mon Mar 02 05:31:46 UTC 2026