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    Searched refs:ValReg (Results 1 - 15 of 15) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86SelectionDAGInfo.cpp 111 unsigned ValReg;
118 ValReg = X86::EAX;
123 ValReg = X86::RAX;
129 ValReg = X86::AX;
134 ValReg = X86::AL;
144 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, dl, AVT),
X86FastISel.cpp 92 bool X86FastEmitStore(EVT VT, unsigned ValReg, X86AddressMode &AM,
487 bool X86FastISel::X86FastEmitStore(EVT VT, unsigned ValReg, X86AddressMode &AM,
507 .addReg(ValReg).addImm(1);
508 ValReg = AndResult;
645 // of FR32 for ValReg. Make sure the register we feed the instruction
650 ValReg = constrainOperandRegClass(Desc, ValReg, Desc.getNumOperands() - 1);
653 addFullAddress(MIB, AM).addReg(ValReg);
697 Register ValReg = getRegForValue(Val);
698 if (ValReg == 0
    [all...]
  /src/external/gpl3/gdb.old/dist/sim/arm/
armcopro.c 1118 static ARMword ValReg[16];
1132 ValReg[BITS (12, 15)] = data;
1155 * data = ValReg[BITS (12, 15)];
1172 *value = ValReg[BITS (16, 19)];
1183 ValReg[BITS (16, 19)] = value;
1200 howlong = ValReg[BITS (0, 3)];
1240 howlong = ValReg[BITS (0, 3)];
1286 ValReg[BITS (0, 3)] = ARMul_Time (state);
  /src/external/gpl3/gcc.old/dist/libphobos/libdruntime/core/internal/
atomic.d 246 enum ValReg = SizedReg!(AX, T);
255 }, [DestReg, ValReg]));
262 enum ValReg = SizedReg!(CX, T);
267 enum ValReg = SizedReg!(DI, T);
279 }, [DestReg, ValReg, ResReg]));
299 enum ValReg = SizedReg!(AX, T);
308 }, [DestReg, ValReg]));
315 enum ValReg = SizedReg!(CX, T);
320 enum ValReg = SizedReg!(DI, T);
332 }, [DestReg, ValReg, ResReg]))
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARC/
ARCOptAddrMode.cpp 426 Register ValReg = IsLoad ? Ldst->getOperand(0).getReg() : Register();
435 if (ValReg && MI->readsVirtualRegister(ValReg))
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsCallLowering.cpp 233 Register extendRegister(Register ValReg, const CCValAssign &VA);
291 Register MipsOutgoingValueHandler::extendRegister(Register ValReg,
296 return MIRBuilder.buildSExt(LocTy, ValReg).getReg(0);
299 return MIRBuilder.buildZExt(LocTy, ValReg).getReg(0);
302 return MIRBuilder.buildAnyExt(LocTy, ValReg).getReg(0);
306 return ValReg;
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
CallLowering.cpp 1052 Register CallLowering::ValueHandler::extendRegister(Register ValReg,
1059 return ValReg;
1063 return ValReg;
1073 return ValReg;
1075 auto MIB = MIRBuilder.buildAnyExt(LocTy, ValReg);
1080 MIRBuilder.buildSExt(NewReg, ValReg);
1085 MIRBuilder.buildZExt(NewReg, ValReg);
LegalizerHelper.cpp 3867 Register ValReg = MI.getOperand(0).getReg();
3869 LLT ValTy = MRI.getType(ValReg);
3884 if (extractParts(ValReg, ValTy, NarrowTy, LeftoverTy, NarrowRegs,
3937 insertParts(ValReg, ValTy, NarrowTy, NarrowRegs,
6763 Register ValReg = MI.getOperand(ValRegIndex).getReg();
6764 const LLT Ty = MRI.getType(ValReg);
6773 MIRBuilder.buildCopy(ValReg, PhysReg);
6775 MIRBuilder.buildCopy(PhysReg, ValReg);
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVExpandAtomicPseudoInsts.cpp 380 MachineBasicBlock *MBB, Register ValReg,
382 BuildMI(MBB, DL, TII->get(RISCV::SLL), ValReg)
383 .addReg(ValReg)
385 BuildMI(MBB, DL, TII->get(RISCV::SRA), ValReg)
386 .addReg(ValReg)
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMAsmPrinter.cpp 1899 Register ValReg = MI->getOperand(1).getReg();
1903 .addReg(ValReg)
1910 .addReg(ValReg)
1913 .addReg(ValReg)
1920 .addReg(ValReg)
1965 Register ValReg = MI->getOperand(1).getReg();
1969 .addReg(ValReg)
1979 .addReg(ValReg)
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64LegalizerInfo.cpp 946 Register ValReg = MI.getOperand(0).getReg();
947 const LLT ValTy = MRI.getType(ValReg);
959 auto Bitcast = MIRBuilder.buildBitcast(NewTy, ValReg);
963 MIRBuilder.buildBitcast(ValReg, NewLoad);
AArch64InstructionSelector.cpp 2630 const Register ValReg = I.getOperand(0).getReg();
2631 const RegisterBank &RB = *RBI.getRegBank(ValReg, MRI, TRI);
2653 IsStore ? NewInst.addUse(ValReg) : NewInst.addDef(ValReg);
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
CallLowering.h 295 Register extendRegister(Register ValReg, CCValAssign &VA,
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUInstructionSelector.cpp 1282 Register ValReg = MI.getOperand(3).getReg();
1285 .addReg(ValReg)
2692 Register ValReg = MI.getOperand(2).getReg();
2696 LLT ValTy = MRI->getType(ValReg);
2701 const RegisterBank *ValRB = RBI.getRegBank(ValReg, *MRI, TRI);
2718 !RBI.constrainGenericRegister(ValReg, *ValRC, *MRI) ||
2743 .addReg(ValReg)
2753 .addReg(ValReg)
AMDGPULegalizerInfo.cpp 2410 Register ValReg = MI.getOperand(0).getReg();
2411 LLT ValTy = MRI.getType(ValReg);
2445 B.buildTrunc(ValReg, WideLoad).getReg(0);
2453 B.buildExtract(ValReg, WideLoad, 0);
2458 WideLoad = Helper.widenWithUnmerge(WideTy, ValReg);

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