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    Searched refs:Variants (Results 1 - 6 of 6) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/X86/
Target.cpp 936 std::vector<InstructionTemplate> Variants;
944 Variants.reserve(NumVariants);
946 Variants.emplace_back(&Instr);
947 Variants.back().setVariableValues(State);
948 // Did we run out of space for variants?
949 return Variants.size() >= NumVariants;
952 assert(Variants.size() == NumVariants &&
953 Variants.size() <= MaxConfigsPerOpcode &&
954 "Should not produce too many variants");
955 return Variants;
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  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
CodeGenSchedule.cpp 575 RecVec Vars = RWDef->getValueAsListOfDefs("Variants");
586 // More may be inferred later when inferring new SchedClasses from variants.
1372 RecVec Variants = SchedRW.TheDef->getValueAsListOfDefs("Variants");
1373 if (any_of(Variants, [PredDef](const Record *R) {
1378 // we're expanding. Consider following RW sequence with two variants
1409 static std::vector<Record *> getAllPredicates(ArrayRef<TransVariant> Variants,
1412 for (auto &Variant : Variants) {
1420 // Populate IntersectingVariants with any variants or aliased sequences of the
1429 std::vector<TransVariant> Variants;
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CodeGenDAGPatterns.cpp 3125 // Generate variants. For example, commutative patterns can match
4439 for (const auto &Variants : ChildVariants)
4440 if (Variants.empty())
4561 // Find the variants of all of our maximal children.
4637 std::vector<std::vector<TreePatternNodePtr>> Variants;
4638 Variants.push_back(std::move(ChildVariants[0])); // Intrinsic id.
4639 Variants.push_back(std::move(ChildVariants[2]));
4640 Variants.push_back(std::move(ChildVariants[1]));
4642 Variants.push_back(std::move(ChildVariants[i]));
4643 CombineChildVariants(N, Variants, OutVariants, CDP, DepVars)
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  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIMachineScheduler.cpp 75 // variants can be tried during the scheduling process.
1946 // if VGPR usage is extremely high, try other good performing variants
1951 Variants[] = {
1961 for (std::pair<SISchedulerBlockCreatorVariant, SISchedulerBlockSchedulerVariant> v : Variants) {
1967 // if VGPR usage is still extremely high, we may spill. Try other variants
1972 Variants[] = {
1982 for (std::pair<SISchedulerBlockCreatorVariant, SISchedulerBlockSchedulerVariant> v : Variants) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AsmParser/
AMDGPUAsmParser.cpp 1562 ArrayRef<unsigned> Variants);
3082 static const unsigned Variants[] = {
3087 return makeArrayRef(Variants);
3090 // What asm variants we should check
3093 static const unsigned Variants[] = {AMDGPUAsmVariants::DEFAULT};
3094 return makeArrayRef(Variants);
3098 static const unsigned Variants[] = {AMDGPUAsmVariants::VOP3};
3099 return makeArrayRef(Variants);
3103 static const unsigned Variants[] = {AMDGPUAsmVariants::SDWA,
3105 return makeArrayRef(Variants);
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  /src/external/apache2/llvm/dist/clang/lib/CodeGen/
CGBuiltin.cpp 813 // Main portable variants.
827 // X86-specific 64-bit variants.
841 // ARM/AArch64-specific ordering variants.
2851 case Builtin::BI_rotl8: // Microsoft variants of rotate left
2862 case Builtin::BI_rotr8: // Microsoft variants of rotate right
3550 "LLVM's __builtin_eh_return only supports 32- and 64-bit variants");
16218 // Intrinsic IDs for row/col variants. 0 if particular layout is unsupported.
16351 std::array<unsigned, 8> Variants;
16355 if (Index >= Variants.size())
16357 return Variants[Index]
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