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    Searched refs:VecRC (Results 1 - 6 of 6) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonVExtract.cpp 139 const auto &VecRC = *MRI.getRegClass(VecR);
140 Align Alignment = HRI.getSpillAlign(VecRC);
146 int FI = MFI.CreateStackObject(HRI.getSpillSize(VecRC), Alignment,
152 unsigned StoreOpc = VecRC.getID() == Hexagon::HvxVRRegClassID
161 unsigned VecSize = HRI.getRegSizeInBits(VecRC) / 8;
HexagonVLIWPacketizer.cpp 879 const TargetRegisterClass *VecRC = HII->getRegClass(MCID, 0, HRI, MF);
880 if (DisableVecDblNVStores && VecRC == &Hexagon::HvxWRRegClass)
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsSEISelLowering.cpp 3336 const TargetRegisterClass *VecRC = nullptr;
3352 VecRC = &Mips::MSA128BRegClass;
3358 VecRC = &Mips::MSA128HRegClass;
3364 VecRC = &Mips::MSA128WRegClass;
3370 VecRC = &Mips::MSA128DRegClass;
3375 Register Wt = RegInfo.createVirtualRegister(VecRC);
3393 Register WdTmp1 = RegInfo.createVirtualRegister(VecRC);
3399 Register WdTmp2 = RegInfo.createVirtualRegister(VecRC);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUInstructionSelector.cpp 2711 const TargetRegisterClass *VecRC = TRI.getRegClassForTypeOnBank(VecTy, *VecRB,
2716 if (!RBI.constrainGenericRegister(VecReg, *VecRC, *MRI) ||
2717 !RBI.constrainGenericRegister(DstReg, *VecRC, *MRI) ||
2726 std::tie(IdxReg, SubReg) = computeIndirectRegIndex(*MRI, TRI, VecRC, IdxReg,
2750 TII.getIndirectGPRIDXPseudo(TRI.getRegSizeInBits(*VecRC), false);
SIISelLowering.cpp 3700 const TargetRegisterClass *VecRC = MRI.getRegClass(SrcReg);
3705 = computeIndirectRegAndOffset(TRI, VecRC, SrcReg, Offset);
3721 TII->getIndirectGPRIDXPseudo(TRI.getRegSizeInBits(*VecRC), true);
3756 TII->getIndirectGPRIDXPseudo(TRI.getRegSizeInBits(*VecRC), true);
3786 const TargetRegisterClass *VecRC = MRI.getRegClass(SrcVec->getReg());
3793 std::tie(SubReg, Offset) = computeIndirectRegAndOffset(TRI, VecRC,
3822 TII->getIndirectGPRIDXPseudo(TRI.getRegSizeInBits(*VecRC), false);
3832 TRI.getRegSizeInBits(*VecRC), 32, false);
3848 Register PhiReg = MRI.createVirtualRegister(VecRC);
3857 TII->getIndirectGPRIDXPseudo(TRI.getRegSizeInBits(*VecRC), false)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64InstructionSelector.cpp 3771 const TargetRegisterClass *VecRC =
3773 if (!VecRC) {

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