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    Searched refs:VecSrc (Results 1 - 5 of 5) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/
InstCombineVectorOps.cpp 1370 Value *VecSrc;
1371 if (match(VecOp, m_BitCast(m_Value(VecSrc))) &&
1374 VecSrc->getType()->isVectorTy() && !ScalarSrc->getType()->isVectorTy() &&
1375 cast<VectorType>(VecSrc->getType())->getElementType() ==
1377 // inselt (bitcast VecSrc), (bitcast ScalarSrc), IdxOp -->
1378 // bitcast (inselt VecSrc, ScalarSrc, IdxOp)
1379 Value *NewInsElt = Builder.CreateInsertElement(VecSrc, ScalarSrc, IdxOp);
  /src/external/apache2/llvm/dist/llvm/lib/IR/
AutoUpgrade.cpp 1271 Value *VecSrc = CI.getOperand(2);
1273 Res = EmitX86Select(Builder, Mask, Res, VecSrc);
1298 Value *VecSrc = CI.getOperand(2);
1300 Res = EmitX86Select(Builder, Mask, Res, VecSrc);
1369 Value *VecSrc = NumArgs == 5 ? CI.getArgOperand(3) :
1373 Res = EmitX86Select(Builder, Mask, Res, VecSrc);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
IRTranslator.cpp 2171 Register VecSrc = getOrCreateVReg(*CI.getArgOperand(1));
2178 MIRBuilder.buildInstr(Opc, {Dst}, {ScalarSrc, VecSrc},
2194 Opc, {DstTy}, {VecSrc}, MachineInstr::copyFlagsFromInstruction(CI));
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUISelLowering.cpp 2161 SDValue VecSrc = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
2165 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecSrc, One);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
DAGCombiner.cpp 12236 SDValue VecSrc = N0.getOperand(0);
12237 EVT VecSrcVT = VecSrc.getValueType();
12244 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, VT, VecSrc,

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