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  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIShrinkInstructions.cpp 248 unsigned Vgpr = TRI.getHWRegIndex(Op.getReg());
251 VgprBase = Vgpr;
252 } else if (VgprBase + i != Vgpr)
SIFoldOperands.cpp 420 // Verify the other operand is a VGPR, otherwise we would violate the
751 // can only accept VGPR or inline immediate. Recreate a reg_sequence with
785 // several reads to do the AGPR->VGPR->AGPR copy.
797 // of exploded copies SGPR->VGPR->AGPR in the copyPhysReg() later,
809 Register Vgpr;
811 Vgpr = VGPRCopies[CopyToVGPR];
813 Vgpr = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);
814 BuildMI(MBB, UseMI, DL, TII->get(AMDGPU::COPY), Vgpr).add(*Def);
815 VGPRCopies[CopyToVGPR] = Vgpr;
819 TII->get(AMDGPU::V_ACCVGPR_WRITE_B32_e64), Tmp).addReg(Vgpr);
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