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  /src/lib/libc/gdtoa/test/
strtodt.c 46 static int W0, W1;
83 if (b.L[W0] != a.L[0] || b.L[W1] != a.L[1]) {
86 line, fname, UL b.L[W0], UL b.L[W1], UL a.L[0], UL a.L[1]);
116 W0 = u.L[0] == 0;
117 W1 = 1 - W0;
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonBitTracker.cpp 311 uint16_t W0 = (Reg[0].Reg != 0) ? getRegBitWidth(Reg[0]) : 0;
323 return rr0(eIMM(im(1), W0), Outputs);
325 return rr0(RegisterCell(W0).fill(0, W0, BT::BitValue::Zero), Outputs);
327 return rr0(RegisterCell(W0).fill(0, W0, BT::BitValue::One), Outputs);
333 RegisterCell RC = RegisterCell::self(Reg[0].Reg, W0);
345 uint16_t RW = W0;
354 uint16_t RW = W0;
370 assert(W0 == 64 && W1 == 32)
    [all...]
HexagonVectorPrint.cpp 75 (Reg >= Hexagon::W0 && Reg <= Hexagon::W15) ||
186 } else if (Reg >= Hexagon::W0 && Reg <= Hexagon::W15) {
187 LLVM_DEBUG(dbgs() << "adding dump for W" << Reg - Hexagon::W0 << '\n');
188 addAsmInstr(MBB, Hexagon::V0 + (Reg - Hexagon::W0) * 2 + 1,
190 addAsmInstr(MBB, Hexagon::V0 + (Reg - Hexagon::W0) * 2,
HexagonISelLoweringHVX.cpp 695 SDValue W0 = isUndef(PredV)
698 Words[IdxW].push_back(Hi32(W0));
699 Words[IdxW].push_back(Lo32(W0));
944 SDValue W0 = extractHvxElementReg(WordVec, W0Idx, dl, MVT::i32, DAG);
946 return DAG.getBitcast(ResTy, W0);
950 SDValue WW = DAG.getNode(HexagonISD::COMBINE, dl, MVT::i64, {W1, W0});
1010 SDValue W0 = DAG.getNode(HexagonISD::VEXTRACTW, dl, MVT::i32, {ShuffV, Zero});
1013 SDValue Vec64 = DAG.getNode(HexagonISD::COMBINE, dl, MVT::v8i8, {W1, W0});
1609 SDValue W0 = extractHvxElementReg(VQ, DAG.getConstant(0, dl, MVT::i32),
1612 return W0;
    [all...]
HexagonRegisterInfo.cpp 86 W0, W1, W2, W3, W4, W5, W6, W7, W8, W9, W10, W11, W12, W13, W14, W15, 0
  /src/crypto/external/apache2/openssl/dist/crypto/sha/asm/
sha512-armv8.pl 370 my ($W0,$W1)=("v16.4s","v17.4s");
390 ld1.32 {$W0},[$Ktbl],#16
401 add.i32 $W0,$W0,@MSG[0]
404 sha256h $ABCD,$EFGH,$W0
405 sha256h2 $EFGH,$abcd,$W0
408 ($W0,$W1)=($W1,$W0); push(@MSG,shift(@MSG));
412 add.i32 $W0,$W0,@MSG[0
    [all...]
sha256-armv4.pl 608 my ($W0,$W1,$ABCD_SAVE,$EFGH_SAVE)=map("q$_",(12..15));
634 vld1.32 {$W0},[$Ktbl]!
646 vadd.i32 $W0,$W0,@MSG[0]
649 sha256h $ABCD,$EFGH,$W0
650 sha256h2 $EFGH,$abcd,$W0
653 ($W0,$W1)=($W1,$W0); push(@MSG,shift(@MSG));
657 vadd.i32 $W0,$W0,@MSG[0
    [all...]
sha1-armv8.pl 250 my ($W0,$W1)=("v20.4s","v21.4s");
276 add.i32 $W0,@Kxx[0],@MSG[0]
283 sha1c $ABCD,$E,$W0 // 0
284 add.i32 $W0,@Kxx[$j],@MSG[2]
298 ($E0,$E1)=($E1,$E0); ($W0,$W1)=($W1,$W0);
307 sha1p $ABCD,$E0,$W0
sha1-armv4-large.pl 624 my ($W0,$W1,$ABCD_SAVE)=map("q$_",(12..14));
658 vadd.i32 $W0,@Kxx[0],@MSG[0]
666 sha1c $ABCD,$E,$W0
667 vadd.i32 $W0,@Kxx[$j],@MSG[2]
681 ($E0,$E1)=($E1,$E0); ($W0,$W1)=($W1,$W0);
690 sha1p $ABCD,$E0,$W0
  /src/crypto/external/bsd/openssl/dist/crypto/sha/asm/
sha512-armv8.pl 364 my ($W0,$W1)=("v16.4s","v17.4s");
382 ld1.32 {$W0},[$Ktbl],#16
393 add.i32 $W0,$W0,@MSG[0]
396 sha256h $ABCD,$EFGH,$W0
397 sha256h2 $EFGH,$abcd,$W0
400 ($W0,$W1)=($W1,$W0); push(@MSG,shift(@MSG));
404 add.i32 $W0,$W0,@MSG[0
    [all...]
sha256-armv4.pl 608 my ($W0,$W1,$ABCD_SAVE,$EFGH_SAVE)=map("q$_",(12..15));
634 vld1.32 {$W0},[$Ktbl]!
646 vadd.i32 $W0,$W0,@MSG[0]
649 sha256h $ABCD,$EFGH,$W0
650 sha256h2 $EFGH,$abcd,$W0
653 ($W0,$W1)=($W1,$W0); push(@MSG,shift(@MSG));
657 vadd.i32 $W0,$W0,@MSG[0
    [all...]
sha1-armv8.pl 248 my ($W0,$W1)=("v20.4s","v21.4s");
272 add.i32 $W0,@Kxx[0],@MSG[0]
279 sha1c $ABCD,$E,$W0 // 0
280 add.i32 $W0,@Kxx[$j],@MSG[2]
294 ($E0,$E1)=($E1,$E0); ($W0,$W1)=($W1,$W0);
303 sha1p $ABCD,$E0,$W0
sha1-armv4-large.pl 624 my ($W0,$W1,$ABCD_SAVE)=map("q$_",(12..14));
658 vadd.i32 $W0,@Kxx[0],@MSG[0]
666 sha1c $ABCD,$E,$W0
667 vadd.i32 $W0,@Kxx[$j],@MSG[2]
681 ($E0,$E1)=($E1,$E0); ($W0,$W1)=($W1,$W0);
690 sha1p $ABCD,$E0,$W0
  /src/crypto/external/bsd/openssl.old/dist/crypto/sha/asm/
sha512-armv8.pl 375 my ($W0,$W1)=("v16.4s","v17.4s");
393 ld1.32 {$W0},[$Ktbl],#16
404 add.i32 $W0,$W0,@MSG[0]
407 sha256h $ABCD,$EFGH,$W0
408 sha256h2 $EFGH,$abcd,$W0
411 ($W0,$W1)=($W1,$W0); push(@MSG,shift(@MSG));
415 add.i32 $W0,$W0,@MSG[0
    [all...]
sha256-armv4.pl 599 my ($W0,$W1,$ABCD_SAVE,$EFGH_SAVE)=map("q$_",(12..15));
624 vld1.32 {$W0},[$Ktbl]!
636 vadd.i32 $W0,$W0,@MSG[0]
639 sha256h $ABCD,$EFGH,$W0
640 sha256h2 $EFGH,$abcd,$W0
643 ($W0,$W1)=($W1,$W0); push(@MSG,shift(@MSG));
647 vadd.i32 $W0,$W0,@MSG[0
    [all...]
sha1-armv8.pl 248 my ($W0,$W1)=("v20.4s","v21.4s");
272 add.i32 $W0,@Kxx[0],@MSG[0]
279 sha1c $ABCD,$E,$W0 // 0
280 add.i32 $W0,@Kxx[$j],@MSG[2]
294 ($E0,$E1)=($E1,$E0); ($W0,$W1)=($W1,$W0);
303 sha1p $ABCD,$E0,$W0
sha1-armv4-large.pl 615 my ($W0,$W1,$ABCD_SAVE)=map("q$_",(12..14));
648 vadd.i32 $W0,@Kxx[0],@MSG[0]
656 sha1c $ABCD,$E,$W0
657 vadd.i32 $W0,@Kxx[$j],@MSG[2]
671 ($E0,$E1)=($E1,$E0); ($W0,$W1)=($W1,$W0);
680 sha1p $ABCD,$E0,$W0
  /src/crypto/external/apache2/openssl/dist/crypto/sm3/
sm3_local.h 97 #define EXPAND(W0, W7, W13, W3, W10) \
98 (P1(W0 ^ W7 ^ ROTATE(W13, 15)) ^ ROTATE(W3, 7) ^ W10)
  /src/crypto/external/bsd/openssl/dist/crypto/sm3/
sm3_local.h 51 #define EXPAND(W0,W7,W13,W3,W10) \
52 (P1(W0 ^ W7 ^ ROTATE(W13, 15)) ^ ROTATE(W3, 7) ^ W10)
  /src/crypto/external/bsd/openssl.old/dist/crypto/sm3/
sm3_local.h 50 #define EXPAND(W0,W7,W13,W3,W10) \
51 (P1(W0 ^ W7 ^ ROTATE(W13, 15)) ^ ROTATE(W3, 7) ^ W10)
  /src/sys/external/isc/atheros_hal/dist/
ah_regdomain.c 50 #define W0(_a) \
54 #define BM1(_fa) { W0(_fa), W1(_fa) }
55 #define BM2(_fa, _fb) { W0(_fa) | W0(_fb), W1(_fa) | W1(_fb) }
57 { W0(_fa) | W0(_fb) | W0(_fc), W1(_fa) | W1(_fb) | W1(_fc) }
59 { W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd),
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64CollectLOH.cpp 262 static_assert(AArch64::W30 - AArch64::W0 + 1 == N_GPR_REGS, "Number of GPRs");
265 if (AArch64::W0 <= Reg && Reg <= AArch64::W30)
266 return Reg - AArch64::W0;
  /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/Disassembler/
BPFDisassembler.cpp 112 BPF::W0, BPF::W1, BPF::W2, BPF::W3, BPF::W4, BPF::W5,
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/Utils/
AArch64BaseInfo.h 31 case AArch64::X0: return AArch64::W0;
71 case AArch64::W0: return AArch64::X0;
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/
HexagonMCInstrInfo.cpp 680 return (VecReg >= Hexagon::W0 && VecReg <= Hexagon::W15) ||
699 2 * (IsRev ? VecRegPair - Hexagon::WR0 : VecRegPair - Hexagon::W0);
710 : Producer - Hexagon::W0;

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