HomeSort by: relevance | last modified time | path
    Searched refs:WB (Results 1 - 10 of 10) sorted by relevancy

  /src/external/lgpl3/gmp/dist/mpn/m88k/
mul_1.s 42 ; pipeline stalls 2 cycles due to WB contention.)
45 ; pipeline stalls 2 cycles due to WB contention and 1 cycle due to latency.)
49 ; 2. Schedule code to avoid WB contention. It might be tempting to move the
50 ; ld instruction in the loops down to save 2 cycles (less WB contention),
92 L1: mul r26,r9,r5 ; low word of product mul_1 WB ld
94 mul r11,r12,r7 ; r11 = prod_0 mul_2 WB mask_1
96 extu r13,r9,16 ; r13 = hi(s1_limb) extu_1 WB mul_1
97 mul r12,r13,r7 ; r12 = prod_1b mul_4 WB extu_1
98 mul r25,r13,r8 ; r25 = prod_2 mul_5 WB mul_2
99 extu r11,r11,16 ; r11 = hi(prod_0) extu_2 WB mul_
    [all...]
  /src/external/gpl3/gcc/dist/gcc/cp/
module.cc 5329 #define WB(X) (bits.b (X))
5333 #define WB_IF(COND, X) WB ((COND) ? (X) : false)
5336 WB (t->base.side_effects_flag);
5337 WB (t->base.constant_flag);
5338 WB (t->base.addressable_flag);
5339 WB (t->base.volatile_flag);
5340 WB (t->base.readonly_flag);
5343 WB (t->base.nowarning_flag);
5348 WB (t->base.nothrow_flag);
5349 WB (t->base.static_flag)
    [all...]
  /src/external/gpl3/gcc.old/dist/gcc/cp/
module.cc 5175 #define WB(X) (b (X))
5178 WB (t->base.side_effects_flag);
5179 WB (t->base.constant_flag);
5180 WB (t->base.addressable_flag);
5181 WB (t->base.volatile_flag);
5182 WB (t->base.readonly_flag);
5185 WB (t->base.nowarning_flag);
5190 WB (t->base.nothrow_flag);
5191 WB (t->base.static_flag);
5194 WB (t->base.public_flag)
    [all...]
  /src/sys/arch/arm/arm/
cpufunc_asm_armv7.S 52 orrlt r0, r0, #TTBR_MPATTR @ MP, cachable (Normal WB)
53 orrge r0, r0, #TTBR_UPATTR @ Non-MP, cacheable, normal WB
152 orrlt r0, r0, #TTBR_MPATTR @ MP, cachable (Normal WB)
153 orrge r0, r0, #TTBR_UPATTR @ Non-MP, cacheable, normal WB
194 mcr p15, 0, r0, c7, c10, 1 @ wb the D-Cache line
233 mcr p15, 0, r0, c7, c10, 1 @ wb the D-Cache to PoC
255 mcr p15, 0, r0, c7, c14, 1 @ wb and inv the D-Cache line to PoC
301 mcr p15, 0, r0, c7, c14, 1 @ wb and inv the D-Cache line
  /src/external/gpl3/binutils/dist/gas/config/
tc-vax.c 193 #define WB (2+-32768)
210 {WF + 1, WB + 1, 3, C (1, 2)},/* W^"foo" 1,1 */
215 {WF + 2, WB + 2, 4, C (2, 2)},/* br.+? brw X 2,1 */
220 {WF, WB, 2, C (3, 2)}, /* brw W^foo 3,1 */
225 {WF, WB, 2, C (4, 2)}, /* acb_ ^Wfoo 4,1 */
230 {WF + 4, WB + 4, 6, C (5, 2)},/* Xob.+2,brb.+3,brw5,1 */
239 #undef WB
  /src/external/gpl3/binutils.old/dist/gas/config/
tc-vax.c 193 #define WB (2+-32768)
210 {WF + 1, WB + 1, 3, C (1, 2)},/* W^"foo" 1,1 */
215 {WF + 2, WB + 2, 4, C (2, 2)},/* br.+? brw X 2,1 */
220 {WF, WB, 2, C (3, 2)}, /* brw W^foo 3,1 */
225 {WF, WB, 2, C (4, 2)}, /* acb_ ^Wfoo 4,1 */
230 {WF + 4, WB + 4, 6, C (5, 2)},/* Xob.+2,brb.+3,brw5,1 */
239 #undef WB
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMBaseInstrInfo.cpp 207 const MachineOperand &WB = isLoad ? MI.getOperand(1) : MI.getOperand(0);
210 Register WBReg = WB.getReg();
304 if (WB.isDead())
3721 UOps += 2; // One for base reg wb, one for write to pc.
  /src/crypto/external/apache2/openssl/dist/test/recipes/30-test_evp_data/
evppkey_kas.txt 11083 k5sGBr4j58V0bb04QE/WB/t/J47iSdyOJ0DPG7mxwHsc9+ClCkMlZ9GGl5moAxIl
  /src/crypto/external/bsd/openssl/dist/test/recipes/30-test_evp_data/
evppkey_kas.txt 11083 k5sGBr4j58V0bb04QE/WB/t/J47iSdyOJ0DPG7mxwHsc9+ClCkMlZ9GGl5moAxIl
  /src/crypto/external/bsd/openssl.old/dist/test/recipes/30-test_evp_data/
evppkey.txt 16690 k5sGBr4j58V0bb04QE/WB/t/J47iSdyOJ0DPG7mxwHsc9+ClCkMlZ9GGl5moAxIl

Completed in 84 milliseconds