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    Searched refs:WBSCL_CLAMP_CBCR (Results 1 - 2 of 2) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
dcn20_dwb.h	92 SRI2(WBSCL_CLAMP_CBCR, WBSCL, inst),\ 214 SF(WBSCL_CLAMP_CBCR, WBSCL_CLAMP_UPPER_CBCR, mask_sh),\ 215 SF(WBSCL_CLAMP_CBCR, WBSCL_CLAMP_LOWER_CBCR, mask_sh),\ 398 uint32_t WBSCL_CLAMP_CBCR;
amdgpu_dcn20_dwb.c	276 REG_UPDATE(WBSCL_CLAMP_CBCR, WBSCL_CLAMP_UPPER_CBCR, 0x3fe); 277 REG_UPDATE(WBSCL_CLAMP_CBCR, WBSCL_CLAMP_LOWER_CBCR, 0x1);

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Indexes created Mon Oct 20 11:09:49 GMT 2025