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  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
dcn20_dwb.h 73 SRI2(WBSCL_MODE, WBSCL, inst),\
171 SF(WBSCL_MODE, WBSCL_MODE, mask_sh),\
172 SF(WBSCL_MODE, WBSCL_OUT_BIT_DEPTH, mask_sh),\
298 type WBSCL_MODE;\
379 uint32_t WBSCL_MODE;
amdgpu_dcn20_dwb.c 261 REG_UPDATE_2(WBSCL_MODE, WBSCL_MODE, params->out_format,

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