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    Searched refs:WR2A_INTR_1 (Results 1 - 2 of 2) sorted by relevancy

/src/sys/arch/luna68k/dev/
sioreg.h	107 #define WR2A_INTR_1 0x04 /* Interrupt Priority: RxA RxB TxA TxB E/SA E/SA */
siotty.c	190 setsioreg(&siosc->sc_ctl[0], WR2A, WR2A_VEC86 | WR2A_INTR_1); 719 setsioreg(sio_a, WR2A, WR2A_VEC86 | WR2A_INTR_1);

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