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    Searched refs:WR5_DTR (Results 1 - 4 of 4) sorted by relevancy

  /src/sys/arch/luna68k/dev/
sioreg.h 142 #define WR5_DTR 0x80 /* Data Terminal Ready [DTR] */
siotty.c 69 WR5_TX8BIT | WR5_TXENBL | WR5_DTR | WR5_RTS, /* Tx */
471 val |= WR5_DTR;
478 wr5 &= ~(WR5_BREAK|WR5_DTR|WR5_RTS);
489 if ((wr5 & WR5_DTR) != 0)
  /src/sys/arch/luna68k/stand/boot/
sioreg.h 160 #define WR5_DTR 0x80 /* Data Terminal Ready [DTR] */
sio.c 230 sioreg(REG(0, WR5), WR5_TX8BIT | WR5_TXENBL | WR5_DTR | WR5_RTS);

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