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    Searched refs:WR5_TXENBL (Results 1 - 5 of 5) sorted by relevancy

  /src/sys/arch/luna68k/stand/boot/
sio.c 230 sioreg(REG(0, WR5), WR5_TX8BIT | WR5_TXENBL | WR5_DTR | WR5_RTS);
246 sioreg(REG(1, WR5), WR5_TX8BIT | WR5_TXENBL);
sioreg.h 154 #define WR5_TXENBL 0x08 /* Transmit Enable */
  /src/sys/arch/luna68k/dev/
sioreg.h 136 #define WR5_TXENBL 0x08 /* Transmit Enable */
lunaws.c 102 WR5_TX8BIT | WR5_TXENBL, /* Tx */
siotty.c 69 WR5_TX8BIT | WR5_TXENBL | WR5_DTR | WR5_RTS, /* Tx */

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