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    Searched refs:WREG32_AND (Results 1 - 7 of 7) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_r600_hdmi.c 379 WREG32_AND(HDMI0_GENERIC_PACKET_CONTROL + offset,
406 WREG32_AND(HDMI0_GC + offset, ~HDMI0_GC_AVMUTE);
461 WREG32_AND(HDMI0_INFOFRAME_CONTROL0 + offset,
495 WREG32_AND(AVIVO_TMDSA_CNTL, ~AVIVO_TMDSA_CNTL_HDMI_EN);
503 WREG32_AND(AVIVO_LVTMA_CNTL, ~AVIVO_LVTMA_CNTL_HDMI_EN);
511 WREG32_AND(DDIA_CNTL, ~DDIA_HDMI_EN);
radeon_evergreen_hdmi.c 402 WREG32_AND(HDMI_GC + offset, ~HDMI_GC_AVMUTE);
430 WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,
434 WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,
489 WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,
radeon_dce3_1_afmt.c 236 WREG32_AND(HDMI0_GC + offset, ~HDMI0_GC_AVMUTE);
radeon_evergreen.c 1753 WREG32_AND(DC_HPDx_INT_CONTROL(hpd), ~DC_HPDx_INT_POLARITY);
4492 WREG32_AND(DC_HPDx_INT_CONTROL(i), DC_HPDx_INT_POLARITY);
radeon.h 2628 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
radeon_si.c 5980 WREG32_AND(DC_HPDx_INT_CONTROL(i),
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu.h 1087 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)

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