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    Searched refs:WREG32_NO_KIQ (Results 1 - 15 of 15) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_mxgpu_ai.c 147 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0),
149 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1),
151 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2),
153 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3),
236 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL), tmp);
289 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL), tmp);
amdgpu_mxgpu_nv.c 149 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW0),
151 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW1),
153 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW2),
155 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW3),
238 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_MAILBOX_INT_CNTL), tmp);
294 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_MAILBOX_INT_CNTL), tmp);
amdgpu_mxgpu_vi.c 330 WREG32_NO_KIQ(mmMAILBOX_CONTROL, reg);
353 WREG32_NO_KIQ(mmMAILBOX_CONTROL, reg);
364 WREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW0, reg);
511 WREG32_NO_KIQ(mmMAILBOX_INT_CNTL, tmp);
541 WREG32_NO_KIQ(mmMAILBOX_INT_CNTL, tmp);
amdgpu_vi.c 98 WREG32_NO_KIQ(mmPCIE_INDEX, reg);
110 WREG32_NO_KIQ(mmPCIE_INDEX, reg);
112 WREG32_NO_KIQ(mmPCIE_DATA, v);
123 WREG32_NO_KIQ(mmSMC_IND_INDEX_11, (reg));
134 WREG32_NO_KIQ(mmSMC_IND_INDEX_11, (reg));
135 WREG32_NO_KIQ(mmSMC_IND_DATA_11, (v));
amdgpu_nbio_v2_3.c 74 WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
amdgpu_nbio_v7_0.c 72 WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
soc15_common.h 47 WREG32_NO_KIQ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value)
amdgpu_ttm.c 1709 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
1710 WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
1716 WREG32_NO_KIQ(mmMM_DATA, value);
2457 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
2458 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
2505 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
2506 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
2507 WREG32_NO_KIQ(mmMM_DATA, value);
amdgpu_navi10_ih.c 243 WREG32_NO_KIQ(reg, tmp);
amdgpu_nbio_v7_4.c 94 WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
amdgpu_gmc_v10_0.c 298 WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, inv_req);
323 WREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng, 0);
amdgpu_vega10_ih.c 428 WREG32_NO_KIQ(reg, tmp);
amdgpu_gmc_v9_0.c 529 WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, inv_req);
551 WREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng, 0);
amdgpu.h 1047 #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
amdgpu_device.c 203 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x80000000);
204 WREG32_NO_KIQ(mmMM_INDEX_HI, pos >> 31);
206 WREG32_NO_KIQ(mmMM_DATA, *buf++);

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