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    Searched refs:WREG32_PLL (Results 1 - 13 of 13) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_clocks.c 407 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);
411 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
417 WREG32_PLL(RADEON_SPLL_CNTL, tmp);
423 WREG32_PLL(RADEON_SPLL_CNTL, tmp);
430 WREG32_PLL(RADEON_M_SPLL_REF_FB_DIV, tmp);
439 WREG32_PLL(RADEON_SPLL_CNTL, tmp);
443 WREG32_PLL(RADEON_SPLL_CNTL, tmp);
449 WREG32_PLL(RADEON_SPLL_CNTL, tmp);
470 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
476 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp)
    [all...]
radeon_rs600.c 273 WREG32_PLL(DYN_PWRMGT_SCLK_LENGTH, dyn_pwrmgt_sclk_length);
285 WREG32_PLL(DYN_SCLK_VOL_CNTL, dyn_sclk_vol_cntl);
292 WREG32_PLL(HDP_DYN_CNTL, hdp_dyn_cntl);
300 WREG32_PLL(MC_HOST_DYN_CNTL, mc_host_dyn_cntl);
307 WREG32_PLL(DYN_BACKBIAS_CNTL, dyn_backbias_cntl);
radeon_legacy_crtc.c 907 WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl);
932 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
1012 WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl);
1038 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
radeon_r520.c 92 WREG32_PLL(0x000D, tmp);
radeon_legacy_tv.c 292 WREG32_PLL(RADEON_PLL_TEST_CNTL, save_pll_test & ~RADEON_PLL_MASK_READ_B);
301 WREG32_PLL(RADEON_PLL_TEST_CNTL, save_pll_test);
763 WREG32_PLL(RADEON_TV_PLL_CNTL, tv_pll_cntl);
radeon_legacy_encoders.c 135 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
673 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
716 WREG32_PLL(RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl);
1607 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
1681 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
radeon_r420.c 213 WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl);
radeon_rv515.c 176 WREG32_PLL(0x000D, tmp);
514 WREG32_PLL(R_00000F_CP_DYN_CNTL,
516 WREG32_PLL(R_000011_E2_DYN_CNTL,
518 WREG32_PLL(R_000013_IDCT_DYN_CNTL,
radeon_combios.c 2998 WREG32_PLL(reg, val);
3115 WREG32_PLL(addr, val);
3128 WREG32_PLL(addr, tmp);
3167 WREG32_PLL(RADEON_MCLK_CNTL,
3171 WREG32_PLL
radeon_r100.c 431 WREG32_PLL(SCLK_CNTL, sclk_cntl);
432 WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
433 WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
2711 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
3909 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
radeon_r300.c 1404 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
radeon.h 2600 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2635 WREG32_PLL(reg, tmp_); \
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu.h 1094 WREG32_PLL(reg, tmp_); \

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