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    Searched refs:WREG32_PLL_P (Results 1 - 5 of 5) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_legacy_crtc.c 239 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
266 WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
880 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
884 WREG32_PLL_P(RADEON_P2PLL_CNTL,
892 WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
896 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
900 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
909 WREG32_PLL_P(RADEON_P2PLL_CNTL,
928 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
961 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL
    [all...]
radeon_legacy_tv.c 762 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVCLK_SRC_SEL_TVPLL);
764 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, RADEON_TVPLL_RESET, ~RADEON_TVPLL_RESET);
768 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVPLL_RESET);
773 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~0xf);
774 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, RADEON_TVCLK_SRC_SEL_TVPLL, ~RADEON_TVCLK_SRC_SEL_TVPLL);
776 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, (1 << RADEON_TVPDC_SHIFT), ~RADEON_TVPDC_MASK);
777 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVPLL_SLEEP);
radeon_legacy_encoders.c 123 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
radeon.h 2630 #define WREG32_PLL_P(reg, val, mask) \
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu.h 1089 #define WREG32_PLL_P(reg, val, mask) \

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