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    Searched refs:WREG32_RCU (Results 1 - 3 of 3) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_sumo_smc.c 85 WREG32_RCU(MCU_M3ARB_PARAMS + (i * 4),
89 WREG32_RCU(MCU_M3ARB_PARAMS + (i * 4),
93 WREG32_RCU(MCU_M3ARB_PARAMS + (i * 4),
127 WREG32_RCU(RCU_ALTVDDNB_NOTIFY, param);
161 WREG32_RCU(RCU_GNB_PWR_REP_TIMER_CNTL, timer_value);
162 WREG32_RCU(RCU_BOOST_MARGIN, pi->sys_info.sclk_dpm_boost_margin);
163 WREG32_RCU(RCU_THROTTLE_MARGIN, pi->sys_info.sclk_dpm_throttle_margin);
164 WREG32_RCU(GNB_TDP_LIMIT, pi->sys_info.gnb_tdp_limit);
165 WREG32_RCU(RCU_SclkDpmTdpLimitPG, pi->sys_info.sclk_dpm_tdp_limit_pg);
209 WREG32_RCU(regoffset, sclk_dpm_tdp_limit)
    [all...]
radeon_sumo_dpm.c 190 WREG32_RCU(RCU_PWR_GATING_SEQ0, 0x10103210);
191 WREG32_RCU(RCU_PWR_GATING_SEQ1, 0x10101010);
193 WREG32_RCU(RCU_PWR_GATING_SEQ0, 0x76543210);
194 WREG32_RCU(RCU_PWR_GATING_SEQ1, 0xFEDCBA98);
205 WREG32_RCU(RCU_PWR_GATING_CNTL, rcu_pwr_gating_cntl);
210 WREG32_RCU(RCU_PWR_GATING_CNTL_2, rcu_pwr_gating_cntl);
215 WREG32_RCU(RCU_PWR_GATING_CNTL_3, rcu_pwr_gating_cntl);
220 WREG32_RCU(RCU_PWR_GATING_CNTL_4, rcu_pwr_gating_cntl);
223 WREG32_RCU(RCU_PWR_GATING_CNTL_5, 0xA02);
235 WREG32_RCU(RCU_PWR_GATING_CNTL, rcu_pwr_gating_cntl)
    [all...]
radeon.h 2610 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))

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