HomeSort by: relevance | last modified time | path
    Searched refs:WREG32_SOC15_RLC (Results 1 - 3 of 3) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfxhub_v1_0.c 79 WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BASE, 0);
80 WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
81 WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
85 WREG32_SOC15_RLC(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
96 WREG32_SOC15_RLC(GC, 0,
101 WREG32_SOC15_RLC(
142 WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
159 WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL, tmp);
164 WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL2, tmp);
176 WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL3, tmp)
    [all...]
amdgpu_gfx_v9_0.c 2424 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
2425 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
2498 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp);
2499 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, 0);
2505 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp);
2510 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, tmp);
3053 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
3251 WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL, 0);
3253 WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL,
3314 WREG32_SOC15_RLC(GC, 0, mmRLC_CP_SCHEDULERS, tmp)
    [all...]
soc15_common.h 118 #define WREG32_SOC15_RLC(ip, inst, reg, value) \

Completed in 15 milliseconds