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    Searched refs:WREG8 (Results 1 - 7 of 7) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_mxgpu_ai.c 42 WREG8(AI_MAIBOX_CONTROL_RCV_OFFSET_BYTE, 2);
47 WREG8(AI_MAIBOX_CONTROL_TRN_OFFSET_BYTE, val ? 1 : 0);
amdgpu_mxgpu_nv.c 42 WREG8(NV_MAIBOX_CONTROL_RCV_OFFSET_BYTE, 2);
47 WREG8(NV_MAIBOX_CONTROL_TRN_OFFSET_BYTE, val ? 1 : 0);
amdgpu.h 1053 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_legacy_tv.c 294 WREG8(RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_TEST_CNTL);
296 WREG8(RADEON_CLOCK_CNTL_DATA + 3, 0);
radeon_r100.c 2905 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2918 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
3812 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3843 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3856 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
radeon_display.c 76 WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
213 WREG8(RADEON_PALETTE_INDEX, 0);
radeon.h 2582 #define WREG8(r, v) bus_space_write_1(rdev->rmmio_bst, rdev->rmmio_bsh, (r), (v))
2587 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))

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