| /src/sys/arch/mips/sibyte/dev/ |
| sbbuswatch.c | 44 #define WRITE_REG(rp, val) mips3_sd((register_t)(rp), (val))
52 WRITE_REG(MIPS_PHYS_TO_KSEG1(A_BUS_L2_ERRORS), 0);
53 WRITE_REG(MIPS_PHYS_TO_KSEG1(A_BUS_MEM_IO_ERRORS), 0);
84 WRITE_REG(MIPS_PHYS_TO_KSEG1(A_BUS_L2_ERRORS), 0);
89 WRITE_REG(MIPS_PHYS_TO_KSEG1(A_BUS_MEM_IO_ERRORS), 0);
|
| sbtimer.c | 62 #define WRITE_REG(rp, val) mips3_sd((register_t)(rp), (val))
139 WRITE_REG(sc->sc_addr_cfg, 0x00); /* XXX */
159 WRITE_REG(sc->sc_addr_cfg, 0x00); /* XXX */
163 WRITE_REG(sc->sc_addr_icnt, (tick/100) - 1); /* XXX */
165 WRITE_REG(sc->sc_addr_icnt, tick - 1); /* XXX */
167 WRITE_REG(sc->sc_addr_cfg, 0x03); /* XXX */
177 WRITE_REG(sc->sc_addr_cfg, 0x03); /* XXX */
200 WRITE_REG(sc->sc_addr_cfg, 0x00); /* XXX */
215 WRITE_REG(sc->sc_addr_cfg, 0x00); /* XXX */
|
| sbwdog.c | 82 #define WRITE_REG(rp, val) (mips3_sd((register_t)(rp), (val)))
126 WRITE_REG(sc->sc_addr + R_SCD_WDOG_CFG, M_SCD_WDOG_ENABLE);
135 WRITE_REG(sc->sc_addr + R_SCD_WDOG_CFG, M_SCD_WDOG_ENABLE);
136 WRITE_REG(sc->sc_addr + R_SCD_WDOG_CFG, 0);
137 WRITE_REG(sc->sc_addr + R_SCD_WDOG_INIT,
139 WRITE_REG(sc->sc_addr + R_SCD_WDOG_CFG, M_SCD_WDOG_ENABLE);
150 WRITE_REG(sc->sc_addr + R_SCD_WDOG_CFG, 0);
161 WRITE_REG(sc->sc_addr + R_SCD_WDOG_INIT,
|
| sbscn.c | 248 #define WRITE_REG(rp, val) (mips3_sd((register_t)(rp), (val)))
264 WRITE_REG(MIPS_PHYS_TO_KSEG1((ch)->ch_sc->sc_addr + 0x2c0), \
266 WRITE_REG(MIPS_PHYS_TO_KSEG1((ch)->ch_sc->sc_addr + 0x2b0), \
296 WRITE_REG(MIPS_PHYS_TO_KSEG1(sc->sc_addr + 0x270), 0);
298 WRITE_REG(MIPS_PHYS_TO_KSEG1(sc->sc_addr + 0x210), 0x0f); /* XXX */
337 WRITE_REG(ch->ch_imr_base, ch->ch_imr);
472 WRITE_REG(ch->ch_imr_base, ch->ch_imr);
486 WRITE_REG(ch->ch_imr_base, ch->ch_imr);
542 WRITE_REG(ch->ch_imr_base, ch->ch_imr);
595 WRITE_REG(ch->ch_imr_base, ch->ch_imr)
[all...] |
| sbjcn.c | 239 #define WRITE_REG(rp, val) (mips3_sd((volatile uint64_t *)(rp), (val)))
1162 WRITE_REG(ch->ch_output_reg, data);
1545 WRITE_REG(MIPS_PHYS_TO_KSEG1(sbjcn_cons_addr + JTAG_CONS_OUTPUT), outbuf);
|
| /src/sys/arch/evbmips/sbmips/ |
| sb1250_icu.c | 94 #define WRITE_REG(rp, val) mips3_sd((register_t)(rp), (val))
173 WRITE_REG(cpu->sb1cpu_imr_base + R_IMR_INTERRUPT_MASK, cpu->sb1cpu_imr_all);
183 WRITE_REG(cpu->sb1cpu_imr_base + R_IMR_MAILBOX_SET_CPU, mbox_mask);
198 WRITE_REG(cpu->sb1cpu_imr_base + R_IMR_MAILBOX_CLR_CPU, mbox_mask);
221 WRITE_REG(cpu->sb1cpu_imr_base + SB1250_I_MAP(i), K_INT_MAP_I0);
226 WRITE_REG(cpu->sb1cpu_imr_base + SB1250_I_MAP(K_INT_WATCHDOG_TIMER_0), K_INT_MAP_NMI);
227 WRITE_REG(cpu->sb1cpu_imr_base + SB1250_I_MAP(K_INT_WATCHDOG_TIMER_1), K_INT_MAP_NMI);
230 WRITE_REG(cpu->sb1cpu_imr_base + R_IMR_INTERRUPT_MASK, cpu->sb1cpu_imr_all);
277 WRITE_REG(imr, imr_all);
280 WRITE_REG(MIPS_PHYS_TO_KSEG1(A_IMR_CPU0_BASE + R_IMR_INTERRUPT_MASK)
[all...] |
| rtc.c | 421 #define WRITE_REG(rp, val) mips3_sd((register_t)(MIPS_PHYS_TO_KSEG1(rp)), (val))
429 WRITE_REG(reg, K_SMB_FREQ_100KHZ);
431 WRITE_REG(reg, 0); /* not in direct mode, no interrupts, will poll */
450 WRITE_REG(reg, (status & M_SMB_ERROR));
478 WRITE_REG(reg, (devaddr >> 8) & 0x7);
485 WRITE_REG(reg, (devaddr & 0xff) & 0xff);
492 WRITE_REG(reg, devaddr & 0xff);
501 WRITE_REG(reg, V_SMB_TT(K_SMB_TT_WR2BYTE) | V_SMB_ADDR(slaveaddr));
503 WRITE_REG(reg, V_SMB_TT(K_SMB_TT_WR1BYTE) | V_SMB_ADDR(slaveaddr));
517 WRITE_REG(reg, V_SMB_TT(K_SMB_TT_RD1BYTE) | V_SMB_ADDR(slaveaddr))
[all...] |
| /src/sys/arch/sbmips/sbmips/ |
| sb1250_icu.c | 94 #define WRITE_REG(rp, val) mips3_sd((register_t)(rp), (val))
173 WRITE_REG(cpu->sb1cpu_imr_base + R_IMR_INTERRUPT_MASK, cpu->sb1cpu_imr_all);
183 WRITE_REG(cpu->sb1cpu_imr_base + R_IMR_MAILBOX_SET_CPU, mbox_mask);
198 WRITE_REG(cpu->sb1cpu_imr_base + R_IMR_MAILBOX_CLR_CPU, mbox_mask);
221 WRITE_REG(cpu->sb1cpu_imr_base + SB1250_I_MAP(i), K_INT_MAP_I0);
226 WRITE_REG(cpu->sb1cpu_imr_base + SB1250_I_MAP(K_INT_WATCHDOG_TIMER_0), K_INT_MAP_NMI);
227 WRITE_REG(cpu->sb1cpu_imr_base + SB1250_I_MAP(K_INT_WATCHDOG_TIMER_1), K_INT_MAP_NMI);
230 WRITE_REG(cpu->sb1cpu_imr_base + R_IMR_INTERRUPT_MASK, cpu->sb1cpu_imr_all);
277 WRITE_REG(imr, imr_all);
280 WRITE_REG(MIPS_PHYS_TO_KSEG1(A_IMR_CPU0_BASE + R_IMR_INTERRUPT_MASK)
[all...] |
| rtc.c | 421 #define WRITE_REG(rp, val) mips3_sd((register_t)(MIPS_PHYS_TO_KSEG1(rp)), (val))
429 WRITE_REG(reg, K_SMB_FREQ_100KHZ);
431 WRITE_REG(reg, 0); /* not in direct mode, no interrupts, will poll */
450 WRITE_REG(reg, (status & M_SMB_ERROR));
478 WRITE_REG(reg, (devaddr >> 8) & 0x7);
485 WRITE_REG(reg, (devaddr & 0xff) & 0xff);
492 WRITE_REG(reg, devaddr & 0xff);
501 WRITE_REG(reg, V_SMB_TT(K_SMB_TT_WR2BYTE) | V_SMB_ADDR(slaveaddr));
503 WRITE_REG(reg, V_SMB_TT(K_SMB_TT_WR1BYTE) | V_SMB_ADDR(slaveaddr));
517 WRITE_REG(reg, V_SMB_TT(K_SMB_TT_RD1BYTE) | V_SMB_ADDR(slaveaddr))
[all...] |
| /src/sys/arch/arm/imx/ |
| imxspi.c | 74 #define WRITE_REG(sc, x, v) \
111 WRITE_REG(sc, CONREG,
116 WRITE_REG(sc, INTREG, (IMXSPI_TYPE(INTR_TC_EN) | IMXSPI(INTR_RR_EN)));
117 WRITE_REG(sc, STATREG, IMXSPI_TYPE(STAT_CLR));
119 WRITE_REG(sc, PERIODREG, 0x0);
168 WRITE_REG(sc, CONREG, contrl);
196 WRITE_REG(sc, CONREG, contrl);
254 WRITE_REG(sc, TXDATA, data);
261 WRITE_REG(sc, CONREG, READ_REG(sc, CONREG) | IMXSPI(CON_XCH));
313 WRITE_REG(sc, CONREG, chipselect)
[all...] |
| /src/sys/dev/pci/ |
| if_txp.c | 376 WRITE_REG(sc, TXP_IER, 0);
377 WRITE_REG(sc, TXP_IMR,
383 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH |
393 WRITE_REG(sc, TXP_IER, 0);
394 WRITE_REG(sc, TXP_IMR,
400 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH |
415 WRITE_REG(sc, TXP_SRR, TXP_SRR_ALL);
417 WRITE_REG(sc, TXP_SRR, 0);
444 WRITE_REG(sc, TXP_IER, ier | TXP_INT_A2H_0);
447 WRITE_REG(sc, TXP_IMR, imr | TXP_INT_A2H_0)
[all...] |
| ubsec.c | 141 #define WRITE_REG(sc,reg,val) \
534 WRITE_REG(sc, BS_CTRL, ctrl);
652 WRITE_REG(sc, BS_STAT, stat); /* IACK */
903 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr +
931 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr +
1882 WRITE_REG(sc, BS_MCR2, q->q_mcr.dma_paddr);
1910 WRITE_REG(sc, BS_MCR4, q->q_mcr.dma_paddr);
2181 WRITE_REG(sc, BS_CTRL, ctrl);
2191 WRITE_REG(sc, BS_CFG, BS_CFG_RNG);
2193 WRITE_REG(sc, BS_INT, BS_INT_DMAINT)
[all...] |
| if_txpreg.h | 627 #define WRITE_REG(sc,reg,val) \
|
| /src/sys/arch/hppa/gsc/ |
| harmonyvar.h | 115 #define WRITE_REG(sc, reg, val) \
|
| harmony.c | 343 WRITE_REG(sc, HARMONY_GAINCTL, GAINCTL_OUTPUT_LEFT_M |
347 WRITE_REG(sc, HARMONY_RESET, RESET_RST);
352 WRITE_REG(sc, HARMONY_RESET, 0);
397 WRITE_REG(sc, HARMONY_OV, 0);
412 WRITE_REG(sc, HARMONY_DSTATUS, DSTATUS_IE);
420 WRITE_REG(sc, HARMONY_DSTATUS, 0);
568 WRITE_REG(sc, HARMONY_PNXTADD,
592 WRITE_REG(sc, HARMONY_RNXTADD,
1054 WRITE_REG(sc, HARMONY_RNXTADD, nextaddr);
1097 WRITE_REG(sc, HARMONY_PNXTADD, nextaddr)
[all...] |
