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Searched refs:WR_LO (Results 1 - 4 of 4) sorted by relevancy

/src/external/gpl3/binutils/dist/opcodes/
mips16-opc.c	182 #define WR_LO INSN_WRITE_LO 282 {"ddiv", ".,x,y", 0xe81e, 0xf81f, RD_2\|RD_3\|WR_HI\|WR_LO, SH, I3, 0, 0 }, 284 {"ddivu", ".,x,y", 0xe81f, 0xf81f, RD_2\|RD_3\|WR_HI\|WR_LO, SH, I3, 0, 0 }, 289 {"div", ".,x,y", 0xe81a, 0xf81f, RD_2\|RD_3\|WR_HI\|WR_LO, SH, I1, 0, 0 }, 291 {"divu", ".,x,y", 0xe81b, 0xf81f, RD_2\|RD_3\|WR_HI\|WR_LO, SH, I1, 0, 0 }, 294 {"dmult", "x,y", 0xe81c, 0xf81f, RD_1\|RD_2\|WR_HI\|WR_LO, SH, I3, 0, 0 }, 295 {"dmultu", "x,y", 0xe81d, 0xf81f, RD_1\|RD_2\|WR_HI\|WR_LO, SH, I3, 0, 0 }, 296 {"drem", ".,x,y", 0xe81e, 0xf81f, RD_2\|RD_3\|WR_HI\|WR_LO, SH, I3, 0, 0 }, 298 {"dremu", ".,x,y", 0xe81f, 0xf81f, RD_2\|RD_3\|WR_HI\|WR_LO, SH, I3, 0, 0 }, 386 {"mult", "x,y", 0xe818, 0xf81f, RD_1\|RD_2\|WR_HI\|WR_LO, SH, I1, 0, 0 } [all...]
micromips-opc.c	`252 #define WR_LO INSN_WRITE_LO 255 #define WR_HILO WR_HI\|WR_LO 945 {"mtlo", "s", 0x00003d7c, 0xffe0ffff, RD_1\|WR_LO, 0, I1, 0, 0 }, 946 {"mtlo", "s,7", 0x0000307c, 0xffe03fff, RD_1\|WR_LO, 0, 0, D32, 0 },`
/src/external/gpl3/binutils.old/dist/opcodes/
mips16-opc.c	182 #define WR_LO INSN_WRITE_LO 282 {"ddiv", ".,x,y", 0xe81e, 0xf81f, RD_2\|RD_3\|WR_HI\|WR_LO, SH, I3, 0, 0 }, 284 {"ddivu", ".,x,y", 0xe81f, 0xf81f, RD_2\|RD_3\|WR_HI\|WR_LO, SH, I3, 0, 0 }, 289 {"div", ".,x,y", 0xe81a, 0xf81f, RD_2\|RD_3\|WR_HI\|WR_LO, SH, I1, 0, 0 }, 291 {"divu", ".,x,y", 0xe81b, 0xf81f, RD_2\|RD_3\|WR_HI\|WR_LO, SH, I1, 0, 0 }, 294 {"dmult", "x,y", 0xe81c, 0xf81f, RD_1\|RD_2\|WR_HI\|WR_LO, SH, I3, 0, 0 }, 295 {"dmultu", "x,y", 0xe81d, 0xf81f, RD_1\|RD_2\|WR_HI\|WR_LO, SH, I3, 0, 0 }, 296 {"drem", ".,x,y", 0xe81e, 0xf81f, RD_2\|RD_3\|WR_HI\|WR_LO, SH, I3, 0, 0 }, 298 {"dremu", ".,x,y", 0xe81f, 0xf81f, RD_2\|RD_3\|WR_HI\|WR_LO, SH, I3, 0, 0 }, 386 {"mult", "x,y", 0xe818, 0xf81f, RD_1\|RD_2\|WR_HI\|WR_LO, SH, I1, 0, 0 } [all...]
micromips-opc.c	`252 #define WR_LO INSN_WRITE_LO 255 #define WR_HILO WR_HI\|WR_LO 945 {"mtlo", "s", 0x00003d7c, 0xffe0ffff, RD_1\|WR_LO, 0, I1, 0, 0 }, 946 {"mtlo", "s,7", 0x0000307c, 0xffe03fff, RD_1\|WR_LO, 0, 0, D32, 0 },`

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