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    Searched refs:WatermarkRow (Results 1 - 11 of 11) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
smu10_driver_if.h 71 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
smu12_driver_if.h 75 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
smu9_driver_if.h 349 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
smu11_driver_if.h 700 WatermarkRowGeneric_t WatermarkRow[WM_COUNT_PP][NUM_WM_RANGES];
smu11_driver_if_navi10.h 910 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/
amdgpu_renoir_ppt.c 783 table->WatermarkRow[WM_DCFCLK][i].MinClock =
786 table->WatermarkRow[WM_DCFCLK][i].MaxClock =
789 table->WatermarkRow[WM_DCFCLK][i].MinMclk =
792 table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
795 table->WatermarkRow[WM_DCFCLK][i].WmSetting = (uint8_t)
800 table->WatermarkRow[WM_SOCCLK][i].MinClock =
803 table->WatermarkRow[WM_SOCCLK][i].MaxClock =
806 table->WatermarkRow[WM_SOCCLK][i].MinMclk =
809 table->WatermarkRow[WM_SOCCLK][i].MaxMclk =
812 table->WatermarkRow[WM_SOCCLK][i].WmSetting = (uint8_t
    [all...]
amdgpu_navi10_ppt.c 1515 table->WatermarkRow[1][i].MinClock =
1519 table->WatermarkRow[1][i].MaxClock =
1523 table->WatermarkRow[1][i].MinUclk =
1527 table->WatermarkRow[1][i].MaxUclk =
1531 table->WatermarkRow[1][i].WmSetting = (uint8_t)
1536 table->WatermarkRow[0][i].MinClock =
1540 table->WatermarkRow[0][i].MaxClock =
1544 table->WatermarkRow[0][i].MinUclk =
1548 table->WatermarkRow[0][i].MaxUclk =
1552 table->WatermarkRow[0][i].WmSetting = (uint8_t
    [all...]
amdgpu_vega20_ppt.c 3058 table->WatermarkRow[1][i].MinClock =
3062 table->WatermarkRow[1][i].MaxClock =
3066 table->WatermarkRow[1][i].MinUclk =
3070 table->WatermarkRow[1][i].MaxUclk =
3074 table->WatermarkRow[1][i].WmSetting = (uint8_t)
3079 table->WatermarkRow[0][i].MinClock =
3083 table->WatermarkRow[0][i].MaxClock =
3087 table->WatermarkRow[0][i].MinUclk =
3091 table->WatermarkRow[0][i].MaxUclk =
3095 table->WatermarkRow[0][i].WmSetting = (uint8_t
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
amdgpu_smu_helper.c 722 table->WatermarkRow[1][i].MinClock =
726 table->WatermarkRow[1][i].MaxClock =
730 table->WatermarkRow[1][i].MinUclk =
734 table->WatermarkRow[1][i].MaxUclk =
738 table->WatermarkRow[1][i].WmSetting = (uint8_t)
743 table->WatermarkRow[0][i].MinClock =
747 table->WatermarkRow[0][i].MaxClock =
751 table->WatermarkRow[0][i].MinUclk =
755 table->WatermarkRow[0][i].MaxUclk =
759 table->WatermarkRow[0][i].WmSetting = (uint8_t
    [all...]
smu_helper.h 48 struct watermark_row_generic_t WatermarkRow[2][4];
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/vega12/
smu9_driver_if.h 593 WatermarkRowGeneric_t WatermarkRow[WM_COUNT_PP][NUM_WM_RANGES];

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