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    Searched refs:WideLoad (Results 1 - 4 of 4) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMParallelDSP.cpp 778 LoadInst *WideLoad = IRB.CreateAlignedLoad(LoadTy, VecPtr, Base->getAlign());
782 MoveBefore(VecPtr, WideLoad);
787 Value *Bottom = IRB.CreateTrunc(WideLoad, Base->getType());
793 Value *Top = IRB.CreateLShr(WideLoad, ShiftVal);
801 << *WideLoad << "\n"
808 std::make_unique<WidenedLoad>(Loads, WideLoad)));
809 return WideLoad;
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPULegalizerInfo.cpp 2442 Register WideLoad;
2444 WideLoad = B.buildLoadFromOffset(WideTy, PtrReg, *MMO, 0).getReg(0);
2445 B.buildTrunc(ValReg, WideLoad).getReg(0);
2452 WideLoad = B.buildLoadFromOffset(WideTy, PtrReg, *MMO, 0).getReg(0);
2453 B.buildExtract(ValReg, WideLoad, 0);
2458 WideLoad = Helper.widenWithUnmerge(WideTy, ValReg);
2460 B.buildLoadFromOffset(WideLoad, PtrReg, *MMO, 0);
AMDGPURegisterBankInfo.cpp 1176 auto WideLoad = B.buildLoadFromOffset(S32, PtrReg, *MMO, 0);
1177 B.buildSExtInReg(MI.getOperand(0), WideLoad, MemSize);
1180 auto WideLoad = B.buildLoadFromOffset(S32, PtrReg, *MMO, 0);
1181 B.buildZExtInReg(MI.getOperand(0), WideLoad, MemSize);
1199 auto WideLoad = B.buildLoadFromOffset(WiderTy, PtrReg, *MMO, 0);
1200 B.buildExtract(MI.getOperand(0), WideLoad, 0);
AMDGPUISelLowering.cpp 1602 SDValue WideLoad = DAG.getExtLoad(
1606 {DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, VT, WideLoad,
1608 WideLoad.getValue(1)},

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