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    Searched refs:WideTy (Results 1 - 14 of 14) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
LegalizerHelper.h 93 LegalizeResult widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
120 /// Use by extending the operand's type to \p WideTy using the specified \p
123 void widenScalarSrc(MachineInstr &MI, LLT WideTy, unsigned OpIdx,
132 /// Def by extending the operand's type to \p WideTy and truncating it back
134 void widenScalarDst(MachineInstr &MI, LLT WideTy, unsigned OpIdx = 0,
160 /// Widen \p OrigReg to \p WideTy by merging to a wider type, padding with
162 Register widenWithUnmerge(LLT WideTy, Register OrigReg);
166 widenScalarMergeValues(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
168 widenScalarUnmergeValues(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
170 widenScalarExtract(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
LegalizerHelper.cpp 1254 void LegalizerHelper::widenScalarSrc(MachineInstr &MI, LLT WideTy,
1257 auto ExtB = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MO});
1268 void LegalizerHelper::widenScalarDst(MachineInstr &MI, LLT WideTy,
1271 Register DstExt = MRI.createGenericVirtualRegister(WideTy);
1286 void LegalizerHelper::moreElementsVectorDst(MachineInstr &MI, LLT WideTy,
1290 MO.setReg(widenWithUnmerge(WideTy, MO.getReg()));
1338 LLT WideTy) {
1351 const int WideSize = WideTy.getSizeInBits();
1360 Register ResultReg = MIRBuilder.buildZExt(WideTy, Src1).getReg(0);
1368 auto ZextInput = MIRBuilder.buildZExt(WideTy, SrcReg)
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  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64PreLegalizerCombiner.cpp 84 LLT WideTy = MRI.getType(WideReg);
86 WideTy.getSizeInBits() - LHSTy.getSizeInBits())
99 LLT WideTy = MRI.getType(WideReg);
103 auto WideZero = Builder.buildConstant(WideTy, 0);
AArch64InstructionSelector.cpp 3817 const LLT WideTy = MRI.getType(SrcReg);
3818 (void)WideTy;
3819 assert(WideTy.getSizeInBits() >= NarrowTy.getSizeInBits() &&
3897 const LLT WideTy = MRI.getType(SrcReg);
3898 (void)WideTy;
3899 assert((WideTy.isVector() || WideTy.getSizeInBits() == 128) &&
3901 assert(WideTy.getSizeInBits() > NarrowTy.getSizeInBits() &&
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/
InductiveRangeCheckElimination.cpp 825 IntegerType *WideTy =
829 dyn_cast<SCEVAddRecExpr>(SE.getSignExtendExpr(AR, WideTy));
831 const SCEV *ExtendedStart = SE.getSignExtendExpr(AR->getStart(), WideTy);
833 SE.getSignExtendExpr(AR->getStepRecurrence(SE), WideTy);
LoopStrengthReduce.cpp 644 Type *WideTy =
646 return isa<SCEVAddRecExpr>(SE.getSignExtendExpr(AR, WideTy));
652 Type *WideTy =
654 return isa<SCEVAddExpr>(SE.getSignExtendExpr(A, WideTy));
660 Type *WideTy =
663 return isa<SCEVMulExpr>(SE.getSignExtendExpr(M, WideTy));
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/
ScalarEvolutionExpander.cpp 1172 Type *WideTy = IntegerType::get(AR->getType()->getContext(), BitWidth * 2);
1174 const SCEV *OpAfterExtend = SE.getAddExpr(SE.getSignExtendExpr(Step, WideTy),
1175 SE.getSignExtendExpr(AR, WideTy));
1177 SE.getSignExtendExpr(SE.getAddExpr(AR, Step), WideTy);
1186 Type *WideTy = IntegerType::get(AR->getType()->getContext(), BitWidth * 2);
1188 const SCEV *OpAfterExtend = SE.getAddExpr(SE.getZeroExtendExpr(Step, WideTy),
1189 SE.getZeroExtendExpr(AR, WideTy));
1191 SE.getZeroExtendExpr(SE.getAddExpr(AR, Step), WideTy);
SimplifyIndVar.cpp 449 auto *WideTy =
454 WideTy, 0);
456 (SE->*Operation)((SE->*Extension)(LHS, WideTy, 0),
457 (SE->*Extension)(RHS, WideTy, 0), SCEV::FlagAnyWrap, 0);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonISelLowering.cpp 1042 MVT WideTy = MVT::getVectorVT(MVT::getIntegerVT(2*ElemTy.getSizeInBits()),
1045 DAG.getSExtOrTrunc(LHS, SDLoc(LHS), WideTy),
1046 DAG.getSExtOrTrunc(RHS, SDLoc(RHS), WideTy), CC);
1100 MVT WideTy = MVT::getVectorVT(MVT::getIntegerVT(2*ElemTy.getSizeInBits()),
1104 DAG.getSelect(dl, WideTy, PredOp,
1105 DAG.getSExtOrTrunc(Op1, dl, WideTy),
1106 DAG.getSExtOrTrunc(Op2, dl, WideTy)),
HexagonISelLoweringHVX.cpp 2291 EVT WideTy = getTypeToTransformTo(*DAG.getContext(), Ty);
2292 assert(WideTy.isSimple());
2293 return Subtarget.isHVXVectorType(WideTy.getSimpleVT(), true);
  /src/external/apache2/llvm/dist/llvm/lib/Analysis/
ScalarEvolution.cpp 1411 Type *WideTy = IntegerType::get(SE->getContext(), BitWidth * 2);
1413 SE->getAddExpr((SE->*GetExtendExpr)(PreStart, WideTy, Depth),
1414 (SE->*GetExtendExpr)(Step, WideTy, Depth));
1415 if ((SE->*GetExtendExpr)(Start, WideTy, Depth) == OperandExtendedStart) {
1653 Type *WideTy = IntegerType::get(getContext(), BitWidth * 2);
1660 WideTy, Depth + 1);
1661 const SCEV *WideStart = getZeroExtendExpr(Start, WideTy, Depth + 1);
1663 getZeroExtendExpr(CastedMaxBECount, WideTy, Depth + 1);
1667 getZeroExtendExpr(Step, WideTy, Depth + 1),
1685 getSignExtendExpr(Step, WideTy, Depth + 1)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPULegalizerInfo.cpp 2440 LLT WideTy = widenToNextPowerOf2(ValTy);
2443 if (!WideTy.isVector()) {
2444 WideLoad = B.buildLoadFromOffset(WideTy, PtrReg, *MMO, 0).getReg(0);
2452 WideLoad = B.buildLoadFromOffset(WideTy, PtrReg, *MMO, 0).getReg(0);
2458 WideLoad = Helper.widenWithUnmerge(WideTy, ValReg);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelDAGToDAG.cpp 1583 MVT WideTy = MVT::getVectorVT(EltTy, 2 * NarrowSize);
1587 SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, WideTy), 0);
1588 return DAG.getTargetInsertSubreg(AArch64::dsub, DL, WideTy, Undef, V64Reg);
AArch64ISelLowering.cpp 8157 MVT WideTy = MVT::getVectorVT(EltTy, 2 * NarrowSize);
8160 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideTy, DAG.getUNDEF(WideTy),
10077 EVT WideTy = WideVec.getValueType();
10079 SDValue Node = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, WideTy, WideVec,
10127 EVT WideTy = WideVec.getValueType();
10129 EVT ExtrTy = WideTy.getVectorElementType();

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