| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorTypes.cpp | 4078 EVT WideVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
4083 unsigned NumElts = WideVT.getVectorNumElements();
4089 WideVT.getVectorNumElements());
4104 SDValue Res = DAG.getMaskedGather(DAG.getVTList(WideVT, MVT::Other),
4317 EVT WideVT = ((NarrowVT == VT0) ? VT1 : VT0);
4318 if (ScalarBits_ToMask >= WideVT.getScalarSizeInBits())
4319 MaskVT = WideVT;
4691 EVT WideVT = EVT::getVectorVT(*DAG.getContext(), EltVT,
4693 if (TLI.isTypeLegal(WideVT) && !N->isStrictFPOpcode()) {
4697 Res = DAG.getNode(Opcode, dl, { WideVT, MVT::Other }
[all...] |
| TargetLowering.cpp | 8398 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getScalarSizeInBits() * 2);
8400 WideVT = EVT::getVectorVT(*DAG.getContext(), WideVT,
8415 } else if (isTypeLegal(WideVT)) {
8416 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
8417 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
8418 SDValue Mul = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
8421 getShiftAmountTy(WideVT, DAG.getDataLayout()));
8423 DAG.getNode(ISD::SRL, dl, WideVT, Mul, ShiftAmt));
8433 if (WideVT == MVT::i16
[all...] |
| DAGCombiner.cpp | 7293 EVT WideVT = EVT::getIntegerVT(Context, WideNumBits);
7294 if (WideVT != MVT::i16 && WideVT != MVT::i32 && WideVT != MVT::i64)
7336 else if (SourceValue.getValueType() != WideVT) {
7337 if (WideVal.getValueType() == WideVT ||
7342 if (SourceValue.getScalarValueSizeInBits() < WideVT.getScalarSizeInBits())
7372 bool Allowed = TLI.allowsMemoryAccess(Context, Layout, WideVT,
7406 if (WideVT != SourceValue.getValueType()) {
7409 SourceValue = DAG.getNode(ISD::TRUNCATE, DL, WideVT, SourceValue)
[all...] |
| LegalizeIntegerTypes.cpp | 926 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VTSize * 2);
928 WideVT = EVT::getVectorVT(*DAG.getContext(), WideVT,
931 LHS = DAG.getSExtOrTrunc(LHS, dl, WideVT);
932 RHS = DAG.getSExtOrTrunc(RHS, dl, WideVT);
934 LHS = DAG.getZExtOrTrunc(LHS, dl, WideVT);
935 RHS = DAG.getZExtOrTrunc(RHS, dl, WideVT);
|
| SelectionDAG.cpp | 10169 EVT WideVT = EVT::getVectorVT(*getContext(), VT.getVectorElementType(),
10171 return getNode(ISD::INSERT_SUBVECTOR, DL, WideVT, getUNDEF(WideVT), N,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 3901 EVT WideVT = MVT::i32;
3902 if (NarrowVT == WideVT)
3928 BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);
3932 SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
3933 DAG.getConstant(0, DL, WideVT), BitShift);
3941 Src2 = DAG.getNode(ISD::SHL, DL, WideVT, Src2,
3942 DAG.getConstant(32 - BitSize, DL, WideVT));
3945 Src2 = DAG.getNode(ISD::OR, DL, WideVT, Src2,
3946 DAG.getConstant(uint32_t(-1) >> BitSize, DL, WideVT));
3949 SDVTList VTList = DAG.getVTList(WideVT, MVT::Other)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 13594 MVT WideVT = WideVec.getSimpleValueType();
13595 if (!WideVT.is256BitVector())
13620 SDValue Shuf = DAG.getVectorShuffle(WideVT, DL, WideVec, DAG.getUNDEF(WideVT),
18136 MVT WideVT = VT;
18138 WideVT = Subtarget.hasDQI() ? MVT::v8i1 : MVT::v16i1;
18139 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideVT,
18140 DAG.getUNDEF(WideVT), V1,
18142 Res = DAG.getNode(X86ISD::KSHIFTR, DL, WideVT, Res,
18239 MVT WideVT = VT
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 7747 EVT WideVT = EVT::getVectorVT(*DAG.getContext(), EltVT, WideNumElts);
7763 Op2 = DAG.getUNDEF(WideVT);
7781 Op1 = DAG.getNode(ISD::BITCAST, DL, WideVT, Op1);
7782 Op2 = DAG.getNode(ISD::BITCAST, DL, WideVT, Op2);
7783 return DAG.getVectorShuffle(WideVT, DL, Op1, Op2, ShuffV);
8317 EVT WideVT = EVT::getVectorVT(*DAG.getContext(), EltVT, WideNumElts);
8326 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WideVT, Ops);
8348 EVT WideVT = Wide.getValueType();
8349 unsigned WideNumElts = WideVT.getVectorNumElements();
8366 SignedConv ? DAG.getUNDEF(WideVT) : DAG.getConstant(0, dl, WideVT)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | 1630 EVT WideVT = RegSeq.getOperand(1)->getValueType(0);
1634 SDValue NV = CurDAG->getTargetExtractSubreg(QSubs[i], dl, WideVT, SuperReg);
1682 EVT WideVT = RegSeq.getOperand(1)->getValueType(0);
1686 SDValue NV = CurDAG->getTargetExtractSubreg(QSubs[i], dl, WideVT,
|
| AArch64ISelLowering.cpp | 10191 EVT WideVT = InVT.widenIntegerVectorElementType(*(DAG.getContext()));
10192 SDValue ExtVec = DAG.getNode(ISD::ANY_EXTEND, DL, WideVT, Vec1);
10195 SDValue HiVec0 = DAG.getNode(AArch64ISD::UUNPKHI, DL, WideVT, Vec0);
10198 SDValue LoVec0 = DAG.getNode(AArch64ISD::UUNPKLO, DL, WideVT, Vec0);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| M68kISelLowering.cpp | 1792 EVT WideVT = WideVal.getValueType();
1819 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 2947 EVT WideVT = MVT::i128;
2964 RTLIB::MUL_I128, WideVT,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVISelLowering.cpp | 3112 MVT WideVT = MVT::getVectorVT(MVT::i8, VecVT.getVectorElementCount());
3113 Vec = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT, Vec);
3114 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, WideVT, Vec, Val, Idx);
3210 MVT WideVT = MVT::getVectorVT(MVT::i8, VecVT.getVectorElementCount());
3211 Vec = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT, Vec);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelLowering.cpp | 1598 EVT WideVT =
1603 Load->getExtensionType(), SL, WideVT, Load->getChain(), BasePtr, SrcValue,
|
