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    Searched refs:X23 (Results 1 - 12 of 12) sorted by relevancy

  /src/sys/external/bsd/gnu-efi/dist/inc/aarch64/
efisetjmp_arch.h 14 UINT64 X23;
  /src/external/gpl3/gdb/dist/sim/testsuite/bfin/
lmu_excpt_illaddr.S 230 X23: [ P1 ] = R1; // Exception should occur here
234 CHECKREG_SYM(r7, X23, r0); // RETX should be value of X23 (HARDCODED ADDR!!)
  /src/external/gpl3/gdb.old/dist/sim/testsuite/bfin/
lmu_excpt_illaddr.S 230 X23: [ P1 ] = R1; // Exception should occur here
234 CHECKREG_SYM(r7, X23, r0); // RETX should be value of X23 (HARDCODED ADDR!!)
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/Utils/
AArch64BaseInfo.h 54 case AArch64::X23: return AArch64::W23;
94 case AArch64::W23: return AArch64::X23;
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64SLSHardening.cpp 173 { "__llvm_slsblr_thunk_x23", AArch64::X23},
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVRegisterInfo.cpp 137 {/*s7*/ RISCV::X23, -9},
RISCVFrameLowering.cpp 153 case /*s7*/ RISCV::X23: return 8;
RISCVISelLowering.cpp 7171 RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27};
8095 .Case("{s7}", RISCV::X23)
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/
AArch64AsmBackend.cpp 647 // X23/X24 pair = 0x00000004,
659 else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 &&
AArch64MCTargetDesc.cpp 124 {codeview::RegisterId::ARM64_X23, AArch64::X23},
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/Disassembler/
AArch64Disassembler.cpp 437 AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24,
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCFrameLowering.cpp 148 {PPC::X23, -72}, \

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