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Searched refs:XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR (Results 1 - 2 of 2) sorted by relevancy

/src/sys/arch/arm/nvidia/
tegra124_xusbpad.c	`274 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR \| 285 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR \| 296 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR \| 310 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD0_CTL1_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR); 311 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD1_CTL1_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR); 312 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD2_CTL1_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR);`
tegra124_xusbpadreg.h	`153 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR __BIT(2)`

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